#14 always block for sequential logic || always block in Verilog || explained with codes and ckt.

[@adilbasu7183]

All your tutorials are more practical.loved the way you explain

[@andyden8501]

Best verilog tutorial. God bless u

[@bijaysah9135]

Good one . Thanks

[@dhanushiyad3756]

Thanks sir.good explaination**

[@MuhammadShahzad-dx5je]

Thank you so much, sir!

[@ComponentByte]

Welcome. Happy learning.

[@ranipore4858]

how out_n=out is not gate in the e.g of both combinational and sequential ?

[@ComponentByte]

out_n = out and out

[@reshmas3714]

Thank you sir

[@preetham36]

is it right to use * in the sensitivity list in the sequential logic???

[@ComponentByte]

Better not to use it. Synthesis software converts verilog code into hardware based on what has been mentioned in sensitivity list.

[@vishalmoladiya2735]

Very nice

[@ComponentByte]

Thank you for your appreciation.

[@preetham36]

at 9:00 both the always block start at the same time ??

[@ComponentByte]

Yes

[@manideepmacharla8128]

for asynchronous u said there is no clk ........then verilog code for d_asynchronous how we will write posedge clk

[@ComponentByte]

Asynchronous means data transfer is not with respect to clock means both are independent. Clock is always there

[@hemanthkumar-xn5vu]

Time 10:00 seq block can also be given like always @ *

[@ComponentByte]

If we write always@* then it won't be called sequential block. It will be a combinational block then. Sequential block means registering the input data. Register works with clock. Hope you got it.

[@abhishekbhadauriya8424]

sir please explain blocking and non blocking assignments.

[@ComponentByte]

I have already uploaded a video on the said topic. Please watch it. If you get any doubt you can always ask your query and I will definitely try to solve your query.

[@abhishekbhadauriya8424]

@@ComponentByte thnqq sir

[@Puffymuffen111]

how two inverter sum up one invertor?

[@ComponentByte]

Whole verilog code has only one inverter. I have divided the whole code into two pieces while explaining and may be this is the confusion.

[@swagatshatabdi]

sir, in synch. sequential ckt every memory elements operates on single clk freq. wheres in async. seq. ckt memory elements involved operates on different clk freq. so when an asynch. clr or preset signal is provided to either of the ckt, irrespective of clk signal, the output of the ckts becomes 0 or 1 respectively. Means asynch clr or preset signals are independent of clk. so in 15:33 why can't we consider reset as a sensitivity variable while creating a synch. seq. ckt? I'm sorry for this long essay😐........

[@swagatshatabdi]

i think 15:33 is the example of synch. seq ckt with synch. clr signal and 16:28 is the example of synch. seq ckt with asynch. clr signal.

[@ComponentByte]

First ckt is for synchronous reset logic where reset depends on clock signal and second ckt is for asynchronous reset logic where reset doesn't depend on clock signal. These are verilog concepts and not exactly digital concepts. This is called synchronous and asynchronous reset and not synchronous or asynchronous sequential ckt. Hope it helps.

[@swagatshatabdi]

@@ComponentByte yes, sir btw thanks for all these videos I'm a fresh btech grad. I don't had any idea, after the graduation what to do? I came across your channel which helped me to set a career goal and motivated me to work hard to be the best. I've completed Digital and now I'm studying verilog. Can you please suggest, from where should I start studying for sys-verilog? Thank YOU....😍 and sir, is it necessary to learn everything of CMOS like abstraction to operation for design & verification role? In a recent interview for DV role they asked me CMOS questions only😓😓

[@ComponentByte]

For verification CMOS knowledge is not required but during interview they may test your B.tech technical knowledge and hence they may ask B.tech level courses. Don't worry, they won't evaluate you based on that knowledge. Whether it's digital design or verification it's always digital and logic skill they are interested in , if it's for freshers job. To learn SV there are plenty of resources available on internet and best is testbench.in. But you need a SV tools to practice it. If you try then free version of questasim will be available in torrent or any other websites. Try for it if you want to learn. If you have verilog knowledge then you can very easily learn SV. SV is more software coding than hardware coding. So learn C ++. It's compulsory for SV.