#18 Timing control in verilog | Delay based, Event based,Level sensitive timing control with example

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Component Byte

Күн бұрын

Пікірлер: 33

@ΧρηστοςΠαλισιδης 2 жыл бұрын

Very exhausting series of videos. Pure teaching skills. Content of 5mins takes 20 mins to be "explained".

@ComponentByte 2 жыл бұрын

All the tutorials are made for fresh learners who knows nothing about verilog. So it's taking time. It might be boring for some but I have tried my best to explain every details possible by me.

@bijaysah9135 4 жыл бұрын

Thank u so much. One day your channel will get million subscribers.

@andyden8501 4 жыл бұрын

Your explanation is always simple and conceptual. Thanks.

@jainammehta6118 4 жыл бұрын

Thank you so much sir please add more exampls that helped lot and also for testbench

@ajaymajhi8429 4 жыл бұрын

Very helpful tutorial. Thank you so much.

@educationpoint7987 4 жыл бұрын

Great explanation. Thanks.

@chintudewan1437 4 жыл бұрын

Excellent. Thanks a lot.

@teketinikhilkumar7905 Жыл бұрын

Can you tell where to practice for questions (mcq+coding)

@ComponentByte Жыл бұрын

Coding practice is not needed if you know how to write code for a logic. We simply cannot remember these codes.Better practice how to develop a logic and draw a circuit diagram.These knowledge are essential. For MCQ, many websites are on internet such as asicworld.com, testbench.in

@mohitkumarpatel8528 Жыл бұрын

In event OR control can we give delay to the procedural assignmnet ????? if so then how is it different from level sensitive timing control???

@ComponentByte Жыл бұрын

Yes, we can give delay. wait is level sensitive so can't be used to design synchronous digital ckt but event or control is edge sensitivity so widely used. But neither delay not wait is syntesizable construct. So both is only used for simulation and not for real hardware design.

@mohitkumarpatel8528 Жыл бұрын

No , EVENT OR CONTROL is not edge triggered. It is edge triggered only when i use posedge.... What if i only use always@(enable) begin If (enable) count =count +1; end Now how is it different from level sensitive timing control????

@ComponentByte Жыл бұрын

Yes, you are correct. Event control usage: 1) multiple variables can be in the sensitivity list 2) can be used to design synchronous digital circuit 3) it doesn't suspend the execution like WAIT statement does.

@adilbasu7183 4 жыл бұрын

Thanks. I request you to upload all the verilog tutorial.

@ComponentByte 4 жыл бұрын

I will upload all the verilog tutorial but one by one. Thanks.

@Nina-qu7qs 3 жыл бұрын

Hi, I have a question regarding zero delay. While explaining always block you said that not to have same output inside multiple always blocks in the same module. For eg. There are two always blocks in a module and both always blocks have same output variable. In such case we can't use this zero delay concept right? Because zero delay applies only for initial block which runs once at sim 0. Just out of curiosity, can we write zero delay even for always block if always block intended to run only once at sim 0(disable after one execution) instead of running the whole time until simulation complete. Thank you!

@ComponentByte 3 жыл бұрын

Hello, always blocks are executed parallely so if we have same output in 2 always block then definitely we will have race around condition even if the code runs only for 0 ns. Simulator may or may not give error but the synthesis tool will definitely gives error because a real time hardware output's can't have 2 different output at same time. I have never tried with always and zero delay(if you have any simulator then you can please try). Because delays are never synthesized. You can always do experiment on your ideas that is how we learn . Wish you a happy learning. Thanks.

@reshmas3714 3 жыл бұрын

Thank you sir

@teketinikhilkumar7905 2 жыл бұрын

sir explain about the line (if statement in named control event) does recieved data gets 1 if the last data packet is 1 what does triggered means there

@ComponentByte 2 жыл бұрын

Trigger means when some inputs are excited. In a series of data if last data packet becomes 1 means last data packet is received by receiver then receiver thinks it received all the data packet as received data signal is triggered.

@smokerji9768 2 жыл бұрын

sir agr zero delay main multiple #0 statment a jay (x,y) ki alag r (w,z) ki alag to kn si execute hu gae pahla ? kyu ka #0 tou dono statment m ha

@ComponentByte 2 жыл бұрын

If multiple #0 delay then it creates race around condition which varies simulator to simulator. So its unpredictable which one executes first. If 4 number of #0 statement comes then the order in which statements are executed can't be predictable. It's random and veries simulator to simulator.

@smokerji9768 2 жыл бұрын

@@ComponentByte ack