180 nm CMOS Inverter Characterization with LT SPICE

[@anandarunakumar6819]

You are very clear. TSMC lib file part is super useful and all the other graphical analysis is very helpful for gaining tool tips. Thank you.

[@SanjayVidhyadharan]

Thabnkyou. You may visit sanjayvidhyadharan.in/all-courses/ you may find few more videos which could be of use to you.

[@mayankgupta460]

Hello sir, First of all great lecture, I did it as an hands on to learn more about the cmos simulation. I have designed an XOR/XNOR Gate and am planning to use the 90nm mosfet for it from evl, this was a great help. Thank you!

[@SanjayVidhyadharan]

Thank you! 😃

[@multiawsome2918]

do you have the 90nm cmos technology parameter files?

[@vamosabv]

Great video which had a lot in such a short time. Thanks!

[@SanjayVidhyadharan]

Glad it was helpful! Thankyou

[@pushpalatha-ui5hh]

Thank u so much sir, very helpful for beginners👌🙏🙏

[@SanjayVidhyadharan]

A more deailed video is avaliable at lesson1 of sanjayvidhyadharan.in/courses/vlsi-design-using-lt-spice/

[@vanlalchaka]

Very helpful sir.. Please keep making video like this..

[@SanjayVidhyadharan]

Sure I will

[@SanjayVidhyadharan]

As of now I am taking Microprocessors course and I am regularly uploading my lectures.

[@vanlalchaka]

@@SanjayVidhyadharan yes I am also interested in microprocessor... Sir one question I am a Ph.D scholar in Mizoram University, my research field is low power VLSI.. As of now We don't have genuine cadences or HSPICE software. So Is there any way to configure/connect FinFET PTM in LP mode, not only in SG mode using LTSPICE??

[@SanjayVidhyadharan]

@@vanlalchaka You can download the required FinFET PTM LP mode and use in LT Spice

[@vanlalchaka]

@@SanjayVidhyadharan thank you so very much sir.. You have been very helpful to me and words cannot explain how grateful I am to you🙏🙏🙏.. Still one doubt! Then, in PTM LP mode the back gate is already negative biased internally??? Because in LTspice we have only three terminal MOSFET.

[@ecestories8816]

Thanks a lot sir! This was really very helpful.

[@SanjayVidhyadharan]

Most welcome!

[@rajeevjaisawal3806]

Great Video sir. Thank you.

[@SanjayVidhyadharan]

Glad it was helpful!

[@LessonsandexerciseswithHayat]

hello sir, when entering a value the transform laplace to the source voltage dependent current source (g) it gives us an error (trouble evaluating laplacian at DC ) what can we do in this situation thank u

[@SanjayVidhyadharan]

You may mail me the asc file at [e-mail]

[@khmailiasameh8347]

thank you thank you, it's very helpful for me !

[@SanjayVidhyadharan]

Thanks a lot. You may visit sanjayvidhyadharan.in/ , you will find lots of videos on various topics arranged in a systematic matter under My courses tab.

[@gufranahmad4778]

Great work. step by step and clear explanation. As per your procedure when I am measuring the leakage current using the curser, it is showing 21.171pA. why this difference, please clarify.

[@SanjayVidhyadharan]

Is the VDD, Width / length of NMOS and PMOS, and model files used excatly the same?. There could be some minor mismatch. Nevertlhess the curret you obseved are in the same pA order.

[@gufranahmad4778]

Thanks for your response. Yes, I have again checked, the same mismatch I am getting. The PMOS leakage current is showing 17.3pA and NMOS is ~ 21pA. Is it because of PDK or due to the simulator? I have recently updated my ltspice. You are truly an enthusiast in knowledge sharing and a great source of learning. I want to be constantly in touch with you and learn from you. please share your email id. Thank you.

[@saieshwar1130]

Design and simulate an inverter for equal rise and fall times. Use length =180nm for pMos and nMOS. Min width to be used is 0,4um for this technology. Calculate the propagation delay, rise time, fall time and power dissipation. The waveforms needs to be presented with the markers

[@SanjayVidhyadharan]

What is the querry?

[@saieshwar1130]

@@SanjayVidhyadharan I need to slove this question using the LT SPICE application can u do a video of it

[@arunkanth55]

Hi Sir Good Morning Great to see somebody spreading knowledge in the best possible way. Can u please guide me in buying a laptop like should I go for an i7 to run these software applications ???

[@SanjayVidhyadharan]

Nice to note that you found the videos helpful. I am managing with a dsktop purchased two years back and hence have not done a good research on laptops avaliable in market. LT spice doesnot require a high-end computer. You may buy a good gaming laptop with good cooling which will give you good performance.

[@arunkanth55]

@@SanjayVidhyadharan ohh ok Sir. Thank you so much for your reply Sir and once again, I wish u very good health and peace for spreading your knowledge.

[@mmuralikrishna5385]

Thank you for posting the video. I have LTspiceXVII version in which I tried to save tsmc018.lib, cmosp.asy, and cmosn.asy files downloaded from your blog and tried to design inverter but could not find the cmos components. to make these library files compatible with the LTspiceXVII version, what changes I need to do. Kindly help me

[@SanjayVidhyadharan]

Ensure you are pasting the lib and sym files in the correct directory. Firstly open a new schematic. Insert any component and see the directory ( Eg. C:Users\Admin\Documents\LTSPICEVII\Lib\Sym) . Then paste the lib in C:Users\Admin\Documents\LTSPICEVII\Lib\sub and sym files in the C:Users\Admin\Documents\LTSPICEVII\Lib\Sym folders)

[@devangkaruskar6626]

i m also facing same problem? can you guide me?

[@sanjayvidhyadharan1175]

@@devangkaruskar6626 Hope your problem is resolved. Else you may call me up on 8447750103

[@devangkaruskar6626]

@@sanjayvidhyadharan1175 thank you sir my problem was resolved

[@عبدالسلامالشرع-ي1ز]

Hello sir, How is the propagation delay calculated in a BCD ADDER circuit?

[@SanjayVidhyadharan]

Concept of Delay is same for all circuits. The delay is usually calculated at 50% point of input-output switching.

[@عبدالسلامالشرع-ي1ز]

@@SanjayVidhyadharan The problem is in the number of inputs and outputs, between which input and output do we take the delay?

[@claudiolarosa8302]

I tried to set mosfet dimensions with other value (but the L always equal to 180nm). In this way I obtain my purpose: a analog working of my circuit. But I have doubt: Can I use any dimension (always greater or equal than 180nm)? I am using for a mosfet a W=190nm, can I to do it? The LTSpice simulator work, but when I want to make my chip with this technology (MOSIS), will this size be accepted? CAn I use different dimension in the same circuit? This serve me for to make an analog circuit. It is possible with this way?

[@SanjayVidhyadharan]

The technolgy specifies the minimum lenght and minimum width. You can always gretaer dimensions it it suits your design.

[@neelutiwari2383]

Very Helpful Thank you sir

[@SanjayVidhyadharan]

Most welcome

[@tvprakadeesh7914]

How channel length modulation can be done

[@SanjayVidhyadharan]

Open the model file as text documnet on note pad. You can see the parameters used in the model

[@kaverihatti686]

Sir can we get the 32nm technology files to work in LTspice

[@SanjayVidhyadharan]

You can serch for PTM files and follow sanjayvidhyadharan.in/lessons/importing-cmoss-60-nm45-nm-22nm-16nm-10-nm-and-7nm-technology-files-into-lt-spice/

[@davidglendaleardenaso8735]

I followed the first few steps of putting the cmos's on sym and then the tsmc018 on sub but the cmos' aren't still showing up on the components

[@SanjayVidhyadharan]

See the video once again carefully. Select the path (folders) for the pasting the sym and lib files. Still if you are not able to resolve, set up a google meet and mail me @ [e-mail]

[@rohithy61]

hello sir, how to find the current flowing across each transistor in ltspice

[@SanjayVidhyadharan]

Run simultaion and then move the cursor on the componet, when the cursor shows circle and an arrow click it for potting current.

[@yuktasrivastava6439]

Sir, i pasted the cmosp and cmosn files in the sym folder. Still I can't find it in the components list.

[@SanjayVidhyadharan]

1.You need to add the tsmc018.lib file in LTspiceIV\lib\sub folder and add SPICE Directive and "INCLUDE tsmc018.lib" SPICE directive in the schematic.

[@SanjayVidhyadharan]

Let me know in case you are still facing a problem.

[@sandrab7711]

Hi...is the problem resolved...I am also facing similar issue...I pasted lib in sub and cmosn and cmosp asy file in sim...and also included the tsmc018.lib library in the schematic.

[@SanjayVidhyadharan]

@@sandrab7711 you need to create the SPICE Directive . INCLUDE tsmc018.lib If the problem is not resolved mail me the asc file at [e-mail].

[@neelutiwari2383]

Sir I am also facing the same problem Please help

[@mousasharif3908]

how to calculate the propagation delay mathematically?

[@SanjayVidhyadharan]

You may go throgh my lectures at sanjayvidhyadharan.in/courses/vlsi-design/

[@preranap8253]

Hello sir, it was an wonderful explanation. Sir I'm actually trying to make a full adder using CMOS tech in orcad PsPice simulation can I use the same tsmc file there, also can I get tsmc7nm anywhere?

[@SanjayVidhyadharan]

I have explained how to import PTM 7 nm in LT SPICE kzbin.info/www/bejne/maTYZ5-ph8iSg6s. in Not sure about PSPICE.

[@ranveerdhawan5187]

Sir I have implemented a current multiplier using Mosfets and its having output of the form K*i1*i2 , where K is UnCoxW/L , now I need to analyse the percentage error but not able to know how to obtain value of K (actually UnCox) from 180nm file , will put W/L as per circuit , can you please help in obtaining K or UnCox

[@SanjayVidhyadharan]

The parameters of the 180 nm devices are mentioned in the spice file. You can verify it by take few sample values of ID, VGS and VDS values form a VGS vs. ID plot.

[@aakankshajha358]

Sir thank you for the video. It was very helpful. Can you please also show the analysis of dynamic CMOS 🙏

[@SanjayVidhyadharan]

Noted. I am presently busy with microprocessor course. I shall do it as soon as i find some spare time. I have explained the concept of dynamic cmos in Presentation on Low Power Techniques for Digital VLSI Design sanjayvidhyadharan.in/blog/digital-vlsi/

[@aakankshajha358]

@@SanjayVidhyadharan Thank you so much sir. That helped a lot!

[@abdelazizlazzaz6826]

Dear Professor, Please confirm me if the LTPSICE support CNTFET. Best wishes

[@SanjayVidhyadharan]

I have explened Importing CMOSS 60 nm, 45 nm, 22nm, 16nm, 10 nm, and 7nm Technology Files into LT SPICE. Same may work for CNFET. No sure if it woul dwork for CNFET. You may try. sanjayvidhyadharan.in/courses/digital-vlsi/

[@claudiolarosa8302]

Great lecture!! I have two questions: 1) how do you understand that the load at the output is 50femtoFarad? It depends on the number of gates you drive, right? I guess then that is a value chosen for the worst case, is it so? 2) Where can I find the definitions for TSMC 65nm technology?

[@SanjayVidhyadharan]

The load is generally a capacitance equivalent to fan-out of four.

[@claudiolarosa8302]

@@SanjayVidhyadharan Thank Sir!

[@gulafshabhatti9410]

its really helpful sir, can you upload an explanation for double balanced Gilbert cell of how to justify output on LT spice. it will be really helpful thank you

[@SanjayVidhyadharan]

Sure, I am presently busy with Microprocessors course. I shall upload it as soon as i find some spare time.

[@krishnakittu6637]

Apart from that can you tell how can we use xilinx netlist in Spice models to see the details of a implementation. Thank you.

[@SanjayVidhyadharan]

Noted. I am presently busy with microprocessor course. I shall do it as soon as i find some spare time

[@tvprakadeesh7914]

Sir could we include short channel effects in ltspice like lamda =1,2

[@SanjayVidhyadharan]

Open the model file as text documnet on note pad. You can see the parameters used in the model

[@aneeshk7396]

Sir, it was a nice video , i have downloaded the tsmc files mentioned and pasted in the respective folders in the C drive. But i could not find the CMOS n and CMOS P symbols in the LT SPICE. what may be the reason sir ? I am using the LTSPICE XVII

[@SanjayVidhyadharan]

You may install Google Chrome remote desktop and call me up on mobile. I will have access your desktop and resolve the issue

[@joelroy663]

@@SanjayVidhyadharan Sir i am also having same problem

[@anirbanganguly3081]

Use nmos4 and pmos4

[@varuntej9349]

@@SanjayVidhyadharan for me also same problem sir..

[@yuktasrivastava6439]

Sir, I want to find the total circuit power dissipation instead of individual components'. Is there any way to do that?

[@SanjayVidhyadharan]

If you have a single power supply source Vdd, which is the case for most of the cmos circuits, the power will be power of the power supply source. You can also do average current of Vdd source multiplied by Vdd, which also should give you same value. The power given by source , will be power dissipated in the whole circuit.

[@saurabhm719]

Sir, I want to make a common gate amplifier using tsmc 180nm with current mirror load. here how would I get lambda for rds, As it is required for gain

[@SanjayVidhyadharan]

You will get the details in the SPICE Model which you have included in the lib/sub folder. Alternatively plot ID-VDS plot for a fixed VGS and from the slope of the region in saturation region, you can compute the VA/Lamda

[@nithyapranav5807]

sir i couldn't measure the power across pmos and nmos.. what would be the reason?

[@SanjayVidhyadharan]

I have uploaded a new video which shall clarify your doubt

[@tanushree3407]

Good explanation sir....will you plz tell me what will be the width for 1um and 10nm technology....here you took 400nm what about other one how to identify

[@SanjayVidhyadharan]

The minimum width is usally specified by the fab lab or in the SPICE Model. For 180 nm gdpk the minimum width is 400nm, for 90nm gdpk he minimum width is 200nm, and for 45 nm gdpk the minmun width is 120 nm. If it is not specfied in the SPICE model which you are using, you may take it as 2.2 to 2.5 times the channel length. Youmay also want to check ITRS specifications

[@sharathcharan3702]

Hello sir, can you upload A CMOS Peak Detect and Hold Circuit With Auto-Adjust Charging Current for NS-Scale Pulse ToF Lidar Application in 45nm CMOS technology using lt spice

[@SanjayVidhyadharan]

I will surely try as and when I get some spare time. In case you are having any difficulty in implementing the circuit you can mail me the details @ [e-mail]

[@SK-pd4qi]

where to get tsmc 0.18 files and how to input it

[@SanjayVidhyadharan]

You can get the tsmc file from sanjayvidhyadharan.in/Downloads/ The installation procedure is explained in the video.

[@vs8950]

what is 180nm? sir which one specifies the 180nm?

[@SanjayVidhyadharan]

180 nm is the CMOS technology node. It is the minimum feature size possible in the technology node. You can have minimum channel length L = 180 nm

[@yathakulasreelekha9528]

Sir I want to know ,how to check 180nm cmos technology in matlab simulink and which version consist which nm cmos technology. Will you pls give me answer to this sir....

[@SanjayVidhyadharan]

Not sure about matlab simulink

[@vedantajaitoo473]

Hello sir, please do a video for multi-stage CMOS amplifiers

[@SanjayVidhyadharan]

Will do soon

[@kadamrahulbalaji6939]

Hello sir, could you explain how we can calculate energy consumption for inverter chain for driving a load ?

[@SanjayVidhyadharan]

Engergy acan be computed by taking the transient response of a desrred time interval and multiplying power with time

[@harshnagar64]

Can it be used as a VLSI project?

[@SanjayVidhyadharan]

If you don't have access to cadence you may use LT SPICE to do VLSI projects. Depends on your institution rules

[@harshnagar64]

@@SanjayVidhyadharansir i m also looking for a simple vlsi project that can be done using LTspice software....where can i find any topic? Any help would be really appreciated.

[@venkatasaicharanjammi7570]

Hello sir Can i import finfet into ltspice How do i use ptm file of finfet in lt spice

[@SanjayVidhyadharan]

The procedure remains same. Get the spice file for finfets. In fact the 7 nm pm files is that of finfet.

[@vasundharagontia3347]

Hello sir, great explanation!! Really helpful for many people. How we are getting 50fF value? Could you provide some link or formula to explain this.

[@SanjayVidhyadharan]

The norm is to use a capacitive load equivalent to Fanout of 4. Gate capacitance needs to be seen and accordingly Cload equivalent to 4 fanout should be used. 50fF was used just as an example.

[@vasundharagontia3347]

@@SanjayVidhyadharan thank you so much for prompt reply. So if we work on the lower node, let say 16nm then this will reduce to what amount??

[@ayushtiwari1391]

very helpful video sir.please tell me that how i draw the leakage power curve of cmos inverter?

[@SanjayVidhyadharan]

Watch the video from 7 min onwards (DC analysis) which indicates the leakage power.

[@ayushtiwari1391]

@@SanjayVidhyadharan thanks a lot sir

[@shalinitatipally824]

Sir is this BSIM model?

[@SanjayVidhyadharan]

Yes. You can have a look at the remarks given in the top of the SPICE model

[@tejaswinikutre8373]

Sir how to design dynamic cmos comparator using ltspice

[@SanjayVidhyadharan]

You can design and cmos circuit in LT SPICE in a similar way as explained in the video. You may refer to my publication link.springer.com/article/10.1007/s10470-019-01487-x on comparator

[@happypurohit5836]

Hello sir, I enjoyed this session it boosted my knowledge. Actually sir I am working on Full adder design in tanner eda but the problem is I can't find 45nm library so can u tell me how I can Implement my design of full adder using 45nm in tanner eda.

[@SanjayVidhyadharan]

I have posted a video on how to import state-of-the-art cmos devices in LT Spice and Cadence. Tanner I have no idea.

[@happypurohit5836]

@@SanjayVidhyadharan Ok Thank you sir..!!🙏

[@yuktasrivastava6439]

Sir, could you please help me in creating lib and asy files for 65nm cmos technology?

[@SanjayVidhyadharan]

Ok. Within a week I shall try to upload a video demonstrating the procedure for importing various technology node library files into LT SPICE

[@yuktasrivastava6439]

@@SanjayVidhyadharan thank you, sir.

[@ranveerdhawan5187]

Sir please tell how to find / calculate the short circuit power

[@SanjayVidhyadharan]

I will try to upload a video on power calculations soon.

[@ranveerdhawan5187]

@@SanjayVidhyadharan Okay sir eagerly waiting for it , Happy Teachers Day sir

[@SanjayVidhyadharan]

I have uploaded a video, which should clarify your doubt

[@ranveerdhawan5187]

@@SanjayVidhyadharan okay sir 👌

[@MukkuPavanKumarPHD]

Sir how to plot SNM of 6T SRAM in LTspice sir

[@SanjayVidhyadharan]

I will try to post a video soon

[@akbarzamani9538]

Hi first thanks for this video. I tried several times to instal cadence virtuoso on my laptop , but I am not successful. Can you make a video about this? Thanks again

[@SanjayVidhyadharan]

Akbar, Cadence is not a free software and hence I wont be able to demonstrate installation.

[@chandbadshah931]

sir files not found bata raha hai tmso18.lib kaise download kare plz help me sir

[@SanjayVidhyadharan]

sanjayvidhyadharan.in/Downloads/

[@krishnakittu6637]

Sir, Thank you it worked. Can you please tell me how can we get the power traces in LT Spice (or) how can we get the output power graph like voltage and current graphs

[@SanjayVidhyadharan]

I think power measurement it is demonstrated in the video. Please watch from 12 minutes onwards.

[@SanjayVidhyadharan]

I have uploaded a video on this aspect

[@aravindanganapathisubraman1173]

sir, can you please explain us how to calculate noise margin in this sir?

[@SanjayVidhyadharan]

You may refer my paper to see how the -1 slope of VTC is used to determine the NM. S. Vidhyadharan, R. Yadav, S. Hariprasad, and S. S. Dan, “An Innovative Ultra-Low Voltage GOTFET based Regenerative-Latch Schmitt Trigger”, Microelectronics Journal, Vol. 104, October 2020. DOI: 10.1016/j.mejo.2020.104879

[@sameeraattar8516]

Sir I need 65nm technology node library can you help me with it sir

[@SanjayVidhyadharan]

Please watch this kzbin.info/www/bejne/maTYZ5-ph8iSg6s for cadence and kzbin.info/www/bejne/iIPGqnh4qp6NZq8 for LT SPICE

[@sameeraattar8516]

@@SanjayVidhyadharan what should be the width for PMOS and NMOS for 65nm

[@ssll123ful]

Please send download link. When I typed it does not work.

[@ssll123ful]

please ignore. I wrongly typed.

[@ssll123ful]

This link is not available.

[@SanjayVidhyadharan]

Please use this link.(Downloads D is capital) sanjayvidhyadharan.in/Downloads

[@ssll123ful]

@@SanjayVidhyadharan Thank you very much. I could download the model file.

[@madhuribabar5478]

Sir I downloaded file tsm180nm.lib n stored in location u told. But when I'm run the program it gives msg couldn't open tsmc189km.lib

[@johnsmiht7776]

Your accent too heavy. Can't understand.

[@SanjayVidhyadharan]

I can't really help in this matter. You may consider making an Indian friend, who could translate it to you.