19 - Describing Multiplexers in Verilog

[@matthewerwine8333]

Thank you so much! My Uni barely goes over verilog, yet all our labs uses it. They really should have a separate class for this, but instead they teach us c++

[@jogemy8545]

I think that loops in verilog aren't synthesizable But the generic one bit mux violates my expectations So, what it the state for my design code from synthesbility if I resorted to loops in

[@Deltax0428]

Rather than using if else for 4to1 mux can we use case statement ?

[@danielarama9328]

WHY NOT ?? module Mux_n_1Bit #(parameter n=8)( input [n-1:0] Data_in, input [$clog2(n)-1:0] sel, output reg f ); integer i; always @(Data_in, sel) begin f = Data_in[sel]; end endmodule