3T DRAM- circuit, read and write operations

𝗗𝗢𝗪𝗡𝗟𝗢𝗔𝗗 𝗦𝗵𝗿𝗲𝗻𝗶𝗸 𝗝𝗮𝗶𝗻 - 𝗦𝘁𝘂𝗱𝘆 𝗦𝗶𝗺𝗽𝗹𝗶𝗳𝗶𝗲𝗱 (𝗔𝗽𝗽) :
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[@sadhi4179]

you just saved my whole life

[@ethanchen3998]

Thank you very much sir for the video, how ever I dont understand why, in the write operation, M2 will be off? Isnt M2 determined by X's voltage?

[@ethanchen3998]

Another question is , If M2 is on, wouldnt M2 cause Cs to go to 1 since then Cs is connected to ground?

[@OutOfRangeDE]

Yes in the writing op m2 is undetermined, or determined by the bit which was saved before. But because m3 is closed it doesnt really matter for x or Bit(inverted). Also there is another capacity between m2 and m3 (gate of m3) which has to be so small by layout config, that it doesnt matter.

[@OutOfRangeDE]

@@ethanchen3998 2nd question: No its not connected to ground since Cs is connected to the gate of m2

[@ShrenikJain]

ANY DOUBT ? ASK ON FB page facebook link : facebook.com/studysimplified/

[@anurondas3853]

Instead of drawing the circuit before hand you should draw it while explaining the circuit. It helps in remembering it.

[@ShrenikJain]

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[@chiragarora2827]

Isn't the threshold voltage only applicable in Gate voltage? I've learnt something new but who knows if it's right or wrong?

[@prithvishetty4171]

No the same threshold voltage or pinch voltage applies for drain to source voltage too. Just look at the o/p characteristics of FET's

[@yashgupta3127]

It is applicable only in gate only but the thing is here it acted as pass transistor and it has a property that it will pass Vd as it is until it is less than Vgs-Vt If Vd is greater than that output will still be Vgs-Vt.I guess your preparing for gate you can refer that 2014 question on pass transistor 5V tha jisme sab gates pe

[@niharikamodi5540]

Here in 3T DRAM for write operation you explained that X = Vdd - Vtn but why you didn't explain same thing for 1T DRAM? ... Am I missing something ? Why it is confusing me ?

[@ttb1513]

You are correct. The same Vtn drop by an Nmos occurs in the dram access transistor. The word line can be boosted above Vdd, like to Vdd+Vtn, such that the full Vdd value from the bit line can be written to the capacitor.

[@VishwanathgoudgOUD]

Thank you for your detailed Explination

[@mcxsaikumar9945]

Good explanation bro,but can u plz tell me steps to design dynamic ram cell (like using 4,2 transistor) instead of 6T,1T.....

[@nahiduzzamansojib3032]

Can you explain the 4T DRAM using CMOS logic

[@ashishagrawal2275]

Thanks bro lec was awesome ur teaching is very good😎😎😎😍😍 thanks bro I was trying to understand this topic from hrs but not but from ur video I have understood thank u

[@ShrenikJain]

ashish agrawal Welcome 😃 Share with your friends too 🙂😃

[@PruthvikaR-t6m]

Bro my exam is in 2 hrs u made this topic so simplified this helped me a lot thank u so much

[@aniketrajapure8251]

very simple and perfect explanation we need these teacherss

[@tabishkhatib8264]

why would m1 need to be on... if it is already on due to word line being active 3:07

[@roopali3369]

too cool bro..thank you ..i can write my internals now

[@shanusingh98]

gazab 6T SRAM, 3T DRAM, 1T DRAM covered my syllabus of gate(Semiconductor memories (digital electronics ece))............ thanks

[@ayushgupta8517]

Great explanation 💯

[@fadi5228]

your bit lines should not be differential ! so it's BL1 and BL2

[@vaibhavvalandikar3913]

Thanks buddy 🙏🏻 .You again saved my ass,tomorrow in my vlsi exam Thanks a alot

[@ShrenikJain]

Welcome 😃

[@rahuljoshi8331]

Today is mine vlsi exam.. hello senior 😅

[@AbhishekSingh-gm6uv]

@@rahuljoshi8331 Tommorow is mine hello senior

[@rahuljoshi8331]

@@AbhishekSingh-gm6uv hahaha😂... Hello junior

[@AbhishekSingh-gm6uv]

@@rahuljoshi8331 😂 apka toh btech khtam ho Gaya hoga?

[@durgae2116]

u jst saved my life.. ive exam tomorrow u explained my half of the syllabus in 15 min.... thanks a lot dude

[@ayushbhujbal3305]

Thanks a lot bro 👊🏻

[@RAJU-ol7cp]

y u were not telling threshold concept in 1 transsistor DRAM?could u expalain that,if u know?

[@Tuftrodgamer]

please draw neatly

[@yashgupta3127]

@4:53 you said bit bar will be forced because of bit ,but as R=0 no current no voltage will be passed toh vo related kaise Hain??

[@absolute___zero]

is 3t-DRAM cell patented? Do you have to pay royalties?

[@freakvencyy2536]

love you bro great tutorial helped a fucking lot

[@ShrenikJain]

Ty 😄😊

[@howzatbangladesh7927]

Thank you brother from MIST

[@ChallaAakash]

Best channel simplified 🔥🔥🔥🔥🔥

[@sahajapinky1385]

thank you sir try to give how it is working on layout point of view also with complete architecture of dram please

[@KamrulHasan-zg8ov]

It is an excellent explanation. Can you please upload the detailed explanation of 4T DRAM ?

[@sarfarazahmedsuri]

6:15: why capacitor(c2) will discharge if m2 and m3 are in on state?

[@VIJAYKUMARN12]

There is a ground path created for C2 through M2-M3 (basically acting like switches), so if C2 is at a higher potential then it will discharge towards ground potential.

[@deeptisingh6543]

thankyou so much!

[@tusharikas5447]

add videos on timinf diagrams of RAMs yaar

[@ShubhamGupta-qo3zb]

What is Vdd and Vtn

[@varshagowda8694]

Excellent sir

[@GaneshJadhav-us7zx]

Thanks! Ur a good teacher

[@aviraldixit1011]

Love you ♥️

[@shuvodev3708]

Good Explanation

[@ShrenikJain]

Ty 😄😊

[@mohanmane1313]

thanks

[@ShrenikJain]

Welcome 😇

[@9bae317]

First 🔥🕺🏿🔥 - Sozo

[@bhagyalakshmis8192]

well explained

[@VIJAYKUMARN12]

Excellent buddy!

[@ShrenikJain]

Ty

[@pritamdss8480]

Make some videos for ROM and RAM

[@ShrenikJain]

+Pritam Dss kzbin.info/www/bejne/mWWxgY2Zm7esjJI

[@rahuljoshi8331]

Awesome bro

[@ShrenikJain]

:)

[@kartikpintu]

thanks

[@ShrenikJain]

Welcome😊 Share with your friends too 😄

[@prajwalit9772]

👍

[@amalkrishna9233]

Thanks

[@ShrenikJain]

welcome :)