4-bit Adder Subtractor Simulation in National Instruments Multisim

We look at a simulation of a 4-bit Adder-Subtractor using National Instruments Multisim. We review the two's complement procedure for representing negative numbers. Then we show how the two's complement procedure can be realized using excluded OR's on the secondary B inputs before they reach the full adders. The second input to those excluded OR's is a new switch which allows us the flip between A+B and A-B. The second step of the two's complement procedure is realized by connecting the new input to the carry-in of the 1's place. Finally we look at what "signed overflow" would look like.