60 - Metastability and Synchronizers

Рет қаралды 7,377

Anas Salah Eddin

Күн бұрын

Пікірлер: 16

@shreyasjadhav1919 Жыл бұрын

Why KZbin doesn't recommend such videos at the top! Very well explained!

@weetabixharry 2 жыл бұрын

This is the only video I have ever found that discusses metastability and synchronization accurately. There is an incredible amount of garbage published online on this topic. It's a shame this video doesn't go deeper and, in particular, discuss the issue of synchronizing > 1 related bits of data.

@黃崇羽 Ай бұрын

Thank you for your awesome explanation!

@socialogic9777 Жыл бұрын

Perfect! I will watch the whole series now..

@Ahmed-i4m1k 10 ай бұрын

شكرا جزاك الله خيرا Thanks

@vigneshkudva3297 Жыл бұрын

Although a synchroniser avoids metastability, it can corrupt the data by settling it into incorrect state. How do we correct it?

@byte_dance 3 жыл бұрын

Excellent video, thanks!

@yaredkokeb5362 2 жыл бұрын

Very good video, surprised this doesn't have more views

@oryyy3219 Жыл бұрын

Very good explaination, should not be this low view count. Anyway great job

@kaptansingh9787 3 ай бұрын

Thanks for such an awesome explanation. I have a question if you can answer. if there is a timing violation and the output goes to the metastable state but do we get the correct output once it comes out of the metastable state or the output can go to either of the logic high or logic low as can be seen the waveform at 4:57?

@anassalaheddin1258 3 ай бұрын

You cannot tell the output of the system after the metastability ends, and you cannot tell for how long it will be in metastable condition.

@dheerajmuppiri1606 10 ай бұрын

excellent

@danielarthur7739 6 ай бұрын

I have a question, Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?

@socialogic9777 Жыл бұрын

Wow! salute

@VarmaKrishnaGare Жыл бұрын

Can't we use a lock up latch instead of a flip flop in the place of a synchronizer ?? Lockup latch with the opposite clock edge connected with the first clock domain does the same job right ?? So, in synchronizers why are we using a flop ? Please explain...