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@tarunkohli80472 жыл бұрын
Please keep up the good work...
@HG-oj2nw Жыл бұрын
schematic @ 11:06 I think the inverter before the final AND should not be located at the output of the last flop. It should be at the other leg of the AND gate after the double-sync waveform @ 4:21 shows that the pulse = (! sampled ) & ack, so it is the "sampled" signal from double-sync cell gets inverted Other than that, great video! I am watching your other videos on apb protoco and glitch free mux and subscribed. Keep up with the good work!!
@emadzokaei5172 Жыл бұрын
Well explained. Thanks
@user-xy5sd8my2e8 ай бұрын
thanks bro! that's very clear. Btw, did you post setup time and hold time video?
@lakshya_garg2 жыл бұрын
Great video, can you please explain the example of continuous changing pulse, how to do CDC on that?
@Electronicspedia2 жыл бұрын
Hi Please watch this video, i have explained kzbin.info/www/bejne/pae0ZomPoaqWbtE
@bhavana_kitchen8 ай бұрын
for the double synch of the ack signal the clock used is clka?
@pranavgupta45522 жыл бұрын
Hi @8.21 you used a +ve edge detection, i think it should be neg. Edge detection ckt at output ..
@Electronicspedia2 жыл бұрын
Curious to know why it has to be negative edge detection ckt?
@pranavgupta45522 жыл бұрын
@@Electronicspedia yes exactly
@TheIanmurphy Жыл бұрын
Is there a limit to how fast the pulses can be in the clkA domain? Like it the pulses were on every 3rd clkA rising edge, would the pulse detector be able to capture them?
@86sheth2 жыл бұрын
how do you feed new value? understand the reason of having 2 muxs on input side. but I think possible OR gate missing on input of 1st mux. agree?
@Electronicspedia2 жыл бұрын
Hi, for the first level mux, there is a PA input. Initially when there is a pulse o/p of first level mux gets set. and it will be cleared only when there is a ack from receiver domain. When 2nd time pulse comes, it will be sampled only if the 1st output has been cleared by ACK, otherwise we will ignore the pulse. Once the Req has been cleared it will be able to take 2nd pulse on the same PA input. There is no need of OR gate. hope this is clear.
@86sheth2 жыл бұрын
@@Electronicspedia actually its not clear. I don't see path/connection to get new value. all above stuff I understand.
@86sheth2 жыл бұрын
@@Electronicspedia is PA would be your new value?
@Electronicspedia2 жыл бұрын
Yes PA is the new value. Everytime new pulse comes in, will be available on PA
@leocn19422 жыл бұрын
@@Electronicspedia for the first level mux, it will be cleared when there is a ack from receiver domain. When 2nd time pulse(PA) comes, it will be sampled, but meaningful only if the 1st output has been cleared by ACK, otherwise we will ignore the pulse. As the previous req pulse is not end.
@sarang5s52 жыл бұрын
Great Video. One feedback. Looks like the edge detection circuit is wrong in your schematic. you are showing +ve edge detection circuit instead of -ve edge in your schematic. Thanks
@Electronicspedia2 жыл бұрын
It looks correct. 7:58 - Here for the positive edge we detect change as follows Posedge = din & ~dout
@jimmychen4308 Жыл бұрын
3:45 why sample b would comes down with clk A posedge? I think it should comes down with clk B posedge
@sourabhjain33462 жыл бұрын
Can you please use a better camera or use it in a different orientation. Video brightness is not consistant.
@Electronicspedia2 жыл бұрын
Thanks for your feedback, will try to take care of it. 👍
@pranavgupta45522 жыл бұрын
Hi another query What is the drawback of handshake technique which motivates us to move to FIFO syncronizers?
@pranavgupta45522 жыл бұрын
More clearly saying why we need fifo syncronizers if we have this handshake technique..
@Electronicspedia2 жыл бұрын
Fifo synchronizers required when we have stream of multibit data to be transferred from one domain to another domain. But with handshake technique we can not transfer multibit and also stream of data.
@reddychowrasta60037 ай бұрын
we can use handahake for multi bit synx also but inly tge thing is we cannot synchronize the stream data with handshake so that was the reason we moves to fido
@user-ky3kg4ut5z Жыл бұрын
Dear sir, can you provide Verilog code for this and the 2 flop synchronizer? Thanx!
@ravichandra17132 жыл бұрын
Sir, how do we handle analog signals in CDC?
@Electronicspedia2 жыл бұрын
Hi, CDC technique is applicable to digital signals, where the value of a signal is either '0' or '1'. Whenever there is a metastability the signal either will be logic 0 or 1. In analog signals we have continuous values for which we don't do CDC analysis.