AC: EC GATE 2019 2M - MOSFET

[@Abhishek_-dd5gk]

great elaboration , you are doing such a great work , Sir.

[@kaushiksengupta4511]

Why is ro considered even when the question says that CLM is neglected ? I thought when CLM is neglected, ro = infinity. Plus they have given a rds value. Are the ro and rds same or different ? Please clarify this!

[@snehab5278]

how could u say m1 and m2 are both in saturation

[@AnkitYadav-zg5zd]

Great question! I think M1 will be in off condition always and the gain will be zero. Because for M1 to be ON, the gate to source voltage should be greater than or equal to the threshold voltage ( i.e. 1 volt here). But here gate to source voltage for M1 is zero (in DC analysis). I think the question is not carefully framed.

[@dastran2731]

@@AnkitYadav-zg5zd bro i think the current mirror forces the M1 transistor to be ON, current mirror itself can be the bias. M1 has no choice it has to be ON

[@AnkitYadav-zg5zd]

@@dastran2731 untill the gate to source voltage of M1 is not greater than threshold voltage, M1 channel is not formed and it behaves as an open circuit. How can current flow through open circuit!

[@dastran2731]

@@AnkitYadav-zg5zd bro take a Mosfet and connect a constant current source across Drain and Source, what happens??? nothing is told about Vg, Vg is open. will current flow or not? i would say yes!

[@dastran2731]

@@AnkitYadav-zg5zd current will make Vg to be at the required value , ya crazy stuff. network theory has some forcing concepts, this is what i think

[@AnkitYadav-zg5zd]

How is M1 ON? Please clarify this sir!

[@dastran2731]

M1 is ON because Vgs1=2V, this we can solve from Id

[@AnkitYadav-zg5zd]

@@dastran2731 how can we conclude that M1 is in saturation?

[@dastran2731]

@@AnkitYadav-zg5zd Just take small nmos circuit with just one loop. Listen carefully, connect a current source across it ( between drain and source) , leave the gate terminal open, now my question is what is the value of Vgs? u can take the help of a computer simulation and see if u don't believe, here Vgs acts as output Id is input. Or I will explain in a different way, say M1 is OFF as u are saying, then what about Mosfet equations in M2 transistor? M2 is in sat anyway. you can contact me if u want to discuss further

[@AnkitYadav-zg5zd]

@@dastran2731 how can i contact you?

[@dastran2731]

@@AnkitYadav-zg5zd u use telegram?

[@dastran2731]

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