DVD - Lecture 8d: Clock Tree Synthesis in EDA Tools

[@BlueMirchi]

Very nice, thank you Please keep doing these videos

[@AdiTeman]

Thank you, I will

[@vivekartist6893]

Hi Professor Adam. Your videos are simply wonderful. Huge fan! One query, could you please provide an example scenario of exclude pin usage for better understanding? Thanks.

[@AdiTeman]

Wow, that is such a great question. It is something I have been teaching for years as an option, but seemed to never have thought about what it's good for! Your question made me look it up. I will say that clock trees are a bigger subject than I discuss in this lecture - much bigger. Every chip has new "surprises" in the clock tree that make you use these different definitions, and every time I have run into one, I say "I'll use that as an example in a lecture on CTS", but by the time it becomes relevant (usually, this is in the middle of a tapeout or other stressful times ;), I totally forget the scenario and why we needed these weird commands... Anyway, back to your question, I found an answer. The general high-level reason is that there can be cases where a net is both on a clock path and a data path. In such a case, you want to buffer the clock part of the net, but not the data part of the net, so you would put "exclude" on the data pins. That is a great explanation, right? Well, the obvious question is "why the heck would a clock net be a data net as well???". And the answer is not too obvious. One answer could be that you may have some observation circuitry on the clock and you treat this as data. But one of the user manuals shows a more common case that actually makes sense and that is the case of a clock divider. A clock divider is just a bunch of flops, where the output of one drives the clock signal of the other with a toggled input. In this case, we have the Q pin of the flop driving a clock net and so it needs to be handled by CTS. Until now, all is good - we want these to be buffered and such. So this is not the case of mixing clock and data. HOWEVER, we perform scan insertion (which I didn't cover in this course), where all flops are connected in a shift register configuration (scan chain) for testing. In this case, the clock net emanating from the Q pin of the divider flop goes to the CK pin of the other divider flop, but also goes to the SI pin of the next flop in the scan chain. This IS a data path and shouldn't be treated as a clock net. So the SI pin should be regarded an EXCLUDE pin. (note, this may be handled inherently by the CTS engine). Thanks for pointing this out so I learned something new.

[@Shahidsoc]

why multiplexers are needed ? to chose different frequencies ? for dynamic volatages and freq ?.

[@AdiTeman]

Hi, Yes, these can be cases for multiplexers on the clock tree. There are actually many cases where you would multiplex several clocks onto the same clock tree. Just as an example that is commonly found on SoCs: We usually provide two clocks: (1) An external reference (from a crystal) with a low frequency (usually less than 100MHz and sometimes much lower) (2) An internally generated clock from a PLL or other clock generator. When we boot the system, the generated clock is not available. It takes time for the PLL to "lock". Additionally, we want a backup in case the PLL doesn't work properly or something like that. So we drive both clocks into a Mux, boot with the external clock, and transfer to the internal clock once it is stable.