DVD - Lecture 4d: Technology Mapping

Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 4 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 4 continues the discussion about logic synthesis, focusing on the algorithms and mechanics that enable logic synthesis and timing optimization.
Lecture 4d goes to the next step of Synthesis - Technology Mapping with minimum tree covering at its heart.
Lecture slides can be found on the EnICS Labs web site at:
enicslabs.com/...
All rights reserved:
Dr. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[@hujiawei5196]

The minimum tree covering algorithm is really just a DP problem

[@AdiTeman]

Thanks!

[@petercheung63]

Hi Sir, do you know how the synthesis actually work? we want to know how to synthesis verilog code into gates by hands. Do you provide private course?

[@AdiTeman]

No, my knowledge about synthesis algorithms is pretty much bound by my explanations here. There are some books that go over the entire flow, such as "Synthesis and optimization of digital circuits" by the great Prof. Giovanni De Micheli (a wonderful guy!). And you can also refer to the open source Yosys project (github.com/YosysHQ/yosys) and see a real synthesizer to the lowest level.

[@petercheung63]

@@AdiTeman thank you Sir