Advanced Process Technologies - Part 2: Fabricating a FinFET

[@SandyMMMM]

I am a layout engineer. Your videos are the best. I want to watch them 10 times. Thank you so much!

[@AdiTeman]

Wow, thanks! Encourages me to make more of these!

[@rabhiselma3994]

Thank you so much really your courses helped me a lot

[@AdiTeman]

Glad I could help!

[@felipemagalhaes3678]

Incredibly informative! Thank you! You helped me a lot to understand it :)

[@AdiTeman]

Glad it was helpful!

[@yushanyeh7187]

Thank you sooooo much!! It really helps a lot !

[@AdiTeman]

You're welcome!

[@sagarkore9648]

Its really helpful thank you so much for such quality content

[@AdiTeman]

Glad you think so!

[@TheKkreddy]

Thank you very much !!!much appreciated ...

[@AdiTeman]

You are welcome!

[@harirao12345]

Outstanding

[@AdiTeman]

Thanks!

[@ndjarnag]

this is good

[@AdiTeman]

Thanks!

[@shantimo6552]

it is very very very helpful

[@AdiTeman]

Glad you think so!

[@rohanyadala9096]

Excellent..

[@AdiTeman]

Thank you! Cheers!

[@adarshitagi8163]

Great video Good Job!

[@AdiTeman]

Thanks!

[@JoeLion55]

As mentioned at 12:20, why do multi-patterned layers have to be unidirectional? Is it because the mask geometry doesn't work, in that you can't really "shift" the pattern in 2 directions? Or, something about how you grow the spacers that only works in one direction at a time?

[@AdiTeman]

Yes, I guess all of the above. Making these tight geometries is really hard (...it's true science fiction. A miracle, even). Doing it in two directions makes it all that much harder (or impossible). One important point is the growth of minimum spaced features (such as gates and fins) in one direction and then using an additional mask (or set of masks) to etch away the parts of the feature that aren't needed in the other direction, but not at minimum spacing. So to have a gate of a certain length, you start with a gate that goes on forever (and you print these at minimum spacing/width across the whole area) and then cut it down to the required size in the other direction. Hope that makes it a bit more clear.

[@vikassh9875]

Can you please make a playlist for these lectures thankyou

[@AdiTeman]

Done! kzbin.info/aero/PLZU5hLL_713x06MZ4OwMwnYGEeszuckZK

[@UmairuddinAshraf]

1:54 pattern our gates or pattern our fins??? Since we are not viewing the finfet substrate from the same angle shown for planer substrate (left figure)

[@AdiTeman]

Yes, in that sentence, I should have said "fins". Thanks for pointing this out. (but I think it is clear, even from the next sentence, where I do say "fins", so not that big a slip :)

[@94D33M]

31:55 why couldn't via sizes just match the metal dimensions so that the connection from one metal to a higher/lower metal doesn't have a bottleneck due to via size?

[@AdiTeman]

So, I'm not 100% sure I understand your question (at least in the context of the timepoint you linked to), but I will try to answer. In general, a VIA is a bit different than a metal layer. Before copper interconnect (pre the "dual damascene" process) it was a completely separate process to implement it. The VIA has a problematic aspect ratio - it is has a relatively large length (height) as compared to its cross section, leading to both high resistance and challenges in filling the hole properly. Therefore, liner layers are used to ensure good connection of the hole to the other layers, and different materials were used that would fill the hole better than aluminum. In any case, special DRCs were devised to ensure yield under mismatch of two masks (e.g., metal overlap on via and via-to-via distance). With newer processes using dual damascene and to lower the overhead of the vias, new via rules and dimensions were introduced which do comply with the metal constraints. However, to ensure yield, other rules are required, such as metal overlap in one dimension. Again, though, VIAs are challenging to manufacture robustly and to ensure alignment and this leads to DRCs that can become a bottleneck.

[@94D33M]

@@AdiTeman Thanks!!

[@fromto6288]

Could tell me why we put HfO2 above the source and drain? How that makes current flow?

[@AdiTeman]

I am not sure what part of the lecture you are relating to (if you want to point me to a particular slide or time, please tell me). But I will try to give a general response to your question. The way that we make a gate oxide is usually through self-alignment. This is true for many (maybe most) very accurate/high resolution features on the chip. I cover this quite extensively in my VLSI course (see this lecture kzbin.info/www/bejne/mKWpnGqgoNBom5Y). Since we need to have a very carefully structured gate oxide and to perfectly align it with the gate metal, we do things like first covering the entire wafer with the oxide and then etch away places where we don't need/want the oxide. In the case of planar transistors, we first build the gate oxide, then the metal gate layer, and then etch away the source and drain areas. In FinFETs, the process is different, as I explain in this lecture series, but to address your question, having an oxide above the source/drain doesn't affect the current. If we want to connect to them, we need to etch away the oxide and drop a contact. But if we don't need to connect to the diffusion (for example when we share a diffusion between two serially connected transistors), the existence of such an oxide doesn't bother us. And in any case, we will build an ILD above the S/D areas to enable deposition of higher interconnect layers (e.g., Metal1). So it doesn't bother the current. Again, if I didn't understand your question, then please refine it and point me to the time in the video that you need clarification for.

[@Akshay-xo5iy]

Hello! Please help me understand how a cell height in a standard cell is defined. What is a metal 2 and what are the tracks?

[@AdiTeman]

Hi Akshay, Please refer to the "DVD" course (kzbin.info/aero/PLZU5hLL_713x0_AV_rVbay0pWmED7992G) and specifically to Lecture 3: kzbin.info/www/bejne/anO9Z6domZilgK8 You can see the entire course content on my web site: www.eng.biu.ac.il/temanad/digital-vlsi-design/

[@saipranavg]

Hi Adi, When we say 7nm device of FinFET type, does it mean the channel length in 7nm ??

[@AdiTeman]

No. In fact, I believe I mention in the lecture (maybe not in this part...) that the channel length has been stuck at around 14nm for quite some time. 7nm is really just a marketing name. Actually, imec, TSMC and other tend to now call this something like "N7" (i.e., "node 7") rather than 7nm, since it really has nothing to do with 7nm...

[@saipranavg]

@@AdiTeman Thank You 🙏

[@yingtang7641]

Hi Adam, I have a question on the doping step in finFET, I dont see it in your animation. isn't it needed?

[@AdiTeman]

Good question. I discuss this in the lecture on Slide 7 (and go into some detail on Slide 20). FinFETs are "fully depleted". In other words, no, there is no doping step. Channel Doping was a huge problem in planar transistors due to RDF (random doping fluctuation), which led to huge process variations. Therefore, the FinFET (and FD-SOI, as well, to the best of my knowledge) are undoped. Instead, threshold voltage tuning is done with the metal gate workfunction. While this is also subject to variation, as far as I know, the main sources of variation in FinFET are LER and LWR. In FD-SOI, the perception is that you can change the threshold voltage through body biasing, and so there is no need for a threshold implant (though this means that you don't have multiple threshold devices...).

[@Jack181996]

@@AdiTeman Hi, I also have a question regarding finfet doping. How are the source and drain contacts made if the channel is intrinsic? Usually you need a very doped region where the contact is then put. Could you explain more about how this is done? And then I have a curiosity. What is the difference between finfets and trigates? Or are they the same thing? Thank you very much!

[@AdiTeman]

@@Jack181996 Hi Jack - good question, though maybe it isn't clear enough in the lecture. First - a small correction. You can have source and drain contacts in a planar technology with an intrinsic channel. The source and drain regions are doped separately from the channel (actually, this is an important self-alignment feature of planar transistors), so the channel doping is not required for contacts. I believe that FD-SOI has such an intrinsic channel. For FinFETs it is, indeed, a different story. The whole middle end of the line is super complicated - going from the transistor up to the backend layers. Specifically, for the contacts, it something like this: - The fins are created adjacent to the channel, but they are really small and problematic to contact to. - In addition, we want to apply stress, which means adding different materials into the S/D regions to improve the channel mobility. - Therefore, an epitaxial layer is built on top of the fins. This enlarges the area to enable contacting the S/D region, enables adding stressors, and is doped to enable an ohmic contact. I hope that kind of clarifies it. With that, watch my explanation in the video again and I think it will become more clear.

[@Jack181996]

@@AdiTeman Thank you, now it is clearer. I have one last curiosity, I hope you can answer me. How is the S/D epitaxial region doped? I imagine with ion implantation with the dummy gate acting as a mask, but I'm not sure

[@qiyu9798]

Professor, is there any link to download your videos? It's very useful for our work

[@AdiTeman]

Hi, You can access all my materials through my faculty website: www.eng.biu.ac.il/temanad/teaching/ Here you can download the PDFs and access the KZbin videos (including the "unlisted" videos, which aren't polished enough to be public).

[@jeffyan4417]

@@AdiTeman sorry professor, but I couldn't find slides any more.

[@AdiTeman]

@@jeffyan4417 go into the links, for example: www.eng.biu.ac.il/temanad/introduction-to-digital-electronic-circuits/

[@xyliu701]

sorry professor, I cannot open this website, is there any network issue of your website? @@AdiTeman

[@gustavderkits8433]

Not rubidium