Very very thank you for this awesome lecture. Everything came naturally one after another.
@christopheracob36892 жыл бұрын
I appreciate hearing the word circuit now unlike others they were pronouncing as cirkyut...
@ececse Жыл бұрын
thankyou sir you made the concept crystal clear
@poojashah61832 жыл бұрын
Thank you sir for making it premier so that we can ask you anything as you are available here
@josedominguez20212 жыл бұрын
Exelente explicación. Muchas gracias!!!
@mayurshah91312 жыл бұрын
Please continue such informative and useful vedios,God bless you
@sarabuvenkatasarayuharika76044 ай бұрын
Excellent explanation sir 👌😌
@mohammadrezajavadi34989 ай бұрын
Excellent explanation
@uhuruplato5262 Жыл бұрын
Well explained.. And very clear.
@saddamalgafsi67215 ай бұрын
3:55 the output should be low instead of high, otherwise very good explanation, keep it up! 😁
@KapilKumar-xz9ip8 ай бұрын
In the last example of gated SR latch with clock here sir use SR latch having NOR Gate and S corresponds to Q' & R corresponds to Q . that's why it is confusing sir, not mentioned it. Now what it again you can understand.
@thisissaroj9412 жыл бұрын
well explained...keep continue to upload so more videos i will support you dear😊
@churchilokech47783 ай бұрын
thank you so much
@koushikpendyala521411 ай бұрын
In Gated SR latch using NOR, when E=1 and S,R =1 then you have said that the case is forbidden, but the inputs that are given are R' and S' so S,R = 0 must be forbidden? Also, The truth table for both Gated SR latch using NOR and NAND is same whereas it is different for SR latch using NOR and NAND? could you explain both these doubts.
@aiore63696 ай бұрын
See the terminal brother... R output is Q not equal to R output is Q'
@shilpapatel7932 жыл бұрын
Great 👏👏👏👏👏
@bhanuprakashagrawal2921 Жыл бұрын
Great concept sir
@omerturnnn8 ай бұрын
Thanks for sharing with us. Can you tell me which software did you use for drawing timing graphics?
@Arj_s92 жыл бұрын
❤️❤️❤️
@janu3858 ай бұрын
Sir, gated sr latch timing and level triggered flip flop. Are both same or is there any difference
@aryansilawal64772 ай бұрын
you said the inputs for sr transparent latch(using nand gates) are active low inputs and others are active high inputs.does this active low or high inputs have any correlation with the outputs we get (Q and Qbar).would you clarify this. its confusing
@ALLABOUTELECTRONICS2 ай бұрын
No, only inputs are active low. Consider the output as it is. For example, to set Q = 1, here for active low inputs S should be 0 and R should be 1. And likewise to reset the latch, S should be 1 and R should be 0. I hope it will clear your doubt.
@gryphon1538Ай бұрын
12:33 is the truth table correct?? coz when s is 1 and r is 0 Q shall be 1 and R shall be 0...we can see when s' is 1 and r' is q is 1 on gated switch which has same nand gate..
@ALLABOUTELECTRONICSАй бұрын
This is a truth table of the SR latch with active low inputs. That means S = 1 and R = 0, it will reset. That means Q = 0. (In active high SR latch, when S = 1, R = 0 then Q = 1)
@flicksonj Жыл бұрын
can i ask a doubt? why S and R have different timing.. sometime it has very duration.. sometime low. I am not an electronics student. its my complementary sub. so do you think is there something I needed to know? the timing is 26:48
@ALLABOUTELECTRONICS Жыл бұрын
Both S and R are different inputs. Many times in a bigger circuits, these inputs are the output of some other circuits. So, they may not be a same. That is why, if you see a time domain signal, then you may notice that, both S and R inputs are changing at the different times. I hope, it will clear your doubt.
@MSQ819 Жыл бұрын
i'm totally confused now
@MdTahsinulIFayed Жыл бұрын
How about now?
@anuraag7075 Жыл бұрын
Same here bro
@xiaoshen194 Жыл бұрын
5 months up... Now?
@user-cr8zn4kx5u10 ай бұрын
Are you alive now
@_JODZILLA_9 ай бұрын
He had massive ACCIDENT while studying in car... RIP 😔
@6blak1975 ай бұрын
3:04 explain about this 2 way switch
@nihar87832 жыл бұрын
can you please provide slides
@swayansamishra22848 ай бұрын
Hello sir at 3:56 how when S=1 then B=1!
@ALLABOUTELECTRONICS8 ай бұрын
Here we are assuming that, initially both S and R is 0. Now, when S is 1, then output of the first NOR gate becomes LOW. So, A = 0. And R is also 0. That means the output of the second NOR gate will become 1. And that's why B = 1. I hope, it will clear your doubt.
@amarsinghsidhu70282 ай бұрын
Sir, Need derivation or source of diagram of SR latch because of confusion: Short connection from NOR gate A to NOR gate 2 vs Connection from NOR gate 2 to NOR gate 1.
@priyashalini6422 Жыл бұрын
Sir what about finite state machines kindly please do that video too
@ALLABOUTELECTRONICS Жыл бұрын
FSM will also be covered soon.
@Ranbir.Bhardwaj Жыл бұрын
A=0 when S=high But How is B=1 when S=high @3:47
@ALLABOUTELECTRONICS Жыл бұрын
It is assumed that, both S and R are 0 initially. And when S becomes 1 momentarily then both A and R will be 0 and hence B becomes 1. I hope, it will clear your doubt.
@Ranbir.Bhardwaj Жыл бұрын
@@ALLABOUTELECTRONICS okay thank you
@bharath_rbp Жыл бұрын
Hello sir, Could you just explain what is active high and active low in brief? because it is getting hard to interpret these words
@ALLABOUTELECTRONICS Жыл бұрын
Active High means the input pin or the input signal will be active when that input is Logic '1'. (the input is active when its logic level is 'High') In the active low , the input pin or the input signal will active when that input is logic '0'. (Input is active when its logic level is 'LOW') I hope, it will clear your doubt.
@cognitive_bits4 ай бұрын
kuch samajh nhi aaya
@ashikrevi Жыл бұрын
Watch some non- indian accent. This is important to your learning too. WTF