Latches and Flip-Flops 1 - The SR Latch

[@latedeveloper7836]

1:30 NOR gate and NAND gate explained 2:25 NOR gate and NAND gate can be used to make an S-R latch 2:35 Cross-coupling of 2 NOR gates in an S-R latch 3:17 Starting state of this S-R latch example 3:55 Resetting the latch 4:17 Pulse removed 4:25 Applying another pulse and implications 5:05 Implications of applying a pulse to S 5:27 Truth table 6:15 Truth table after applying a set pulse 6:25 Truth table after removing the set pulse 7:15 Race condition 8:00 Active High S-R Latch Explained 8:41 Truth table for Active High S-R Latch 9:20 Active Low S-R Latch (i.e. built from NAND gates) 9:44 Forbidden state of the S-R latch built from NAND gates 10:00 Summary 10:37 Switch bounce problem 11:37 Examples of applications of an S-R latch

[@DanilKarlos]

Finally a perfect explanation with a great and easy to understand accent

[@realmzakaria]

Thanks god it's not in indian accent lol or I would fail man!

[@TheAnnoor]

that's racist

[@jszlauko]

No, it's not racist, as he is just saying that the indian accent is very hard to understand, and I agree.

[@IchCharacter]

You mean that our hearing is racist or our ability to understand certain accents is racist? I guess it's very racist that we haven't started making every language and culture an obligatory subject in school yet, huh? We can afford the extra decade. I hope you better understand all Scottish and Irish accents perfectly, otherwise you're a total biggot. And God help you if there's any African accent you don't understand flawlessly!

[@mimdim925]

Indian english in general is different to british english. i dont speak english as a first language, and british english was the english i had to study, so from a non english speaking background a subset of english i learnt is easier to understand than one with a different set of english. that being said some indian youtubers are very helpful

[@samsonmayeem8409]

I am offering my college degree i got confused today in my computer architecture lecture.With this video i am now a good "comprehender"! wishe that i get a lot of your tutorials to enhances most troubling concepts. you are a great teacher. Thank you.

[@D34THM45T3R]

One the clearest most concise videos out there on SR Latches. Much appreciated !

[@ΧρυσοβαλαντηςΤασιοπουλος]

The question is who's running first the upper nor gate? or the lower nor gate from the previous state in order to go to the next state of q and q not?

[@FirstLast-vs1gv]

Great video thanks! Best part is that you switch the inputs in realtime.

[@ComputerScienceLessons]

Thanks a million

[@mth32871]

This is one of the best explanations of the SR latch that I have ever seen.

[@ComputerScienceLessons]

Kind of you to say so. Thanks :)KD

[@heitorodorizzibeltrame5811]

Wow! I couldn't understand this latch until this video. Thank you so much for your great job!

[@Bizzon666]

Great video! I have already learned the function of SR latch, but I was confused by different realizations of the circuit which are perfectly explained here.

[@SnoozeDog]

This video better than any other explanation, short to the point

[@supermariozaken]

Are you kidding? 12 minutes for something that can be explained in 3

[@javerianadeem5556]

Marquis Chan nice

[@youngcitybandit]

@@supermariozaken 3 minutes? if anything he covered the topic quite efficiently but it was only long due to him slowly speaking for his viewers.

[@johanhendriks]

@@supermariozaken where's your 3 minute explanation? Please share a link

[@humanbeing1149]

the game lumber tycoon 2 has these stuff (roblox)

[@E4E]

This is a great series of videos on latches & flip-flops!

[@ninjaweave8779]

Explained in a nice easy to understand way really well, thanks very much! Wish I just watched this video first instead of wasting hours of reading my textbook

[@ComputerScienceLessons]

It's great to know it was useful. Thanks for commenting.

[@unway1841]

This video is clear and concise. Well done, sir.

[@ComputerScienceLessons]

Thank you :)KD

[@hanif2285]

You've got a subscriber mate, You are wayyyy better than my teacher, and your explanation directly goes to the permanent area of brain. Great Job, well done, God Bless You!!!!! Keep up the good work!

[@ComputerScienceLessons]

Thanks for the lovely comment. Please spread the word about my channel. :)KD

[@deepjyotisinha1879]

i was thinking of getting my degree abroad .Thank god i didnt .Thanks dad for not letting me

[@EduardoSanchez-lu2sv]

Great video! It helped me understand latches just fine . The example at the end was great. It is definitely amazing what simple binary logic can do !

[@Laptevwalrus]

The hardest part how cross linking works is unexplained.

[@madd_v2522]

Thanks so much!! I felt like in a scene in Snatch and Jason Stateham teaching me digital electronics

[@ComputerScienceLessons]

It's not a tickling competition. :)KD

[@madd_v2522]

@@ComputerScienceLessons it's an unlicensed boxing match! :D

[@BIRDYCODYT]

Really thankful for this!

[@ComputerScienceLessons]

You're welcome :)KD

[@markfinn825]

I find an SR latch made of an OR Gate , AND Gate , Inverter combo very useful. The OR Gate output is fed to one AND Gate input. The other AND Gate input is fed by the inverter output. The inverter input is the Reset input. One of the OR Gate inputs is fed by the AND Gate output which is also the output of the Latch. The other OR Gate input is the Set input. There are no disallowed states and the output is always predictable even at power up.

[@juand3250]

Wow, a really good explanation. Thank you

[@ComputerScienceLessons]

You're very welcome :)KD

[@TomThomasVempala]

Thank you so much.. best explanation and example

[@ComputerScienceLessons]

Thank you :)KD

[@timlindberg3833]

According to IEC 61131-3, Set have priority in SR-latches. Meaning if both inputs are 1 then Q = 1. RS-latch has priority on R. Older standard this was reverse, R had priority in a SR-latch, and if i remember correctly it was because of the order instruction list was executed. This is thanks to the deterministic nature of PLCs 🤓

[@ComputerScienceLessons]

Indeed. The technology evolves very quickly :)KD

[@knowhowstube4751]

you change my life sir

[@x7Degreesx]

Thank you so much . I thought id never understand it

[@edwardduda4222]

Thank you for making this video. My professor is terrible at explaining these latches.

[@rinnegansr5980]

great explanation!

[@ComputerScienceLessons]

TY :)KD

[@shivashissengupta8830]

perfect explanation , best of all love you dude , thanks a lot again

[@ComputerScienceLessons]

Thank you for lovely comment :)KD

[@fd2444]

This better than my 2 hour lecture

[@ComputerScienceLessons]

Glad to help :)KD

[@theman83744]

A great video. Helped a lot

[@ComputerScienceLessons]

Thanks for the comment

[@EducaLK]

Excellent explanation,

[@ComputerScienceLessons]

You are very kind. Thank you :)KD

[@examguidepublishers3623]

@@ComputerScienceLessons I always share your content to my students. Thank your corporation .😀

[@EducaLK]

@@ComputerScienceLessons I always share your contents to my students 😀

[@buhaissy]

excellent. thank you

[@ComputerScienceLessons]

You are welcome :) KD

[@zhoucindy3204]

exactly what I want. Thank you

[@ComputerScienceLessons]

Thanks for saying so :)

[@bensmith9253]

Just what I was looking for!

[@SusantaTewari]

With NOR SR latch, I don't understand how the gates can output a signal initially. You need two input signals for the NOR gate but initially there is only one input for each of the NOR gate (R and S) since the Q and NOT Q outputs are not generated yet. Can NOR gates output a signal given only one input signal?

[@FManVybzsta]

I Loooove this , thank you very much

[@WarringFighter]

no one: my 7 yo ass when told to not play with the lights: 10:47

[@ComputerScienceLessons]

That'll be the morning after feeling.

[@abysmal111]

This video helped me so much. Thank you! =D

[@ThefamousMrcroissant]

What is so confusing about these is their initial state. The seemingly concurrent nature of the schematic makes it pretty hard to deduce what exactly is expected of it without further explanation.

[@ComputerScienceLessons]

Perhaps a later video of this series will help :)KD

[@ThefamousMrcroissant]

@@ComputerScienceLessons Oh no, I'm familiar with them. I'm just describing what I found confusing when I was first presented with these. Also keep up the excellent work by publishing free educational content like this.

[@iverpunayan7308]

Thank you sir good job

[@anterkod]

Thank you, good explanation :)

[@Montv3]

nice, this was really helpfull

[@RenoxxCaregivers-jm5zj]

Hi, can you do a video on Finite State Machine, please.

[@corruptelites5600]

awesome

[@ComputerScienceLessons]

TY

[@nanditasatish5614]

thankyou

[@ComputerScienceLessons]

You're welcome :)KD

[@EriAirlangga]

So what happens if you feedback the output of an inverter to its input?

[@matthewcohen315]

Is it possible to do with XOR?

[@muthazzoe]

You sir are of great help, to that I say Good Day! I have an exam in two days based on latches and flip flops, I will get back to you on how much I got

[@ComputerScienceLessons]

Please do. The best of luck to you :)KD

[@muthazzoe]

@@ComputerScienceLessons hey boss, got a 67% the whole exam wasnt about flip flops but I'm sure all those questions about them that I did were correct. Thanks again!

[@trashmann1081]

lifesaver, thanks so much

[@GandalfBerngtsson]

Of the two outputs, is Q said to be the output of the latch?

[@ComputerScienceLessons]

Strictly speaking, there are 2 outputs, Q and Q prime. But it's reasonable to consider Q as the output and Q prime as it's opposite.

[@mechvex8726]

5:20 PULSES

[@granthoffman610]

I joined the marines because I didn’t want to go to college now I’m in the middle of the desert trying to teach this to myself

[@pianopat6924]

Prayers!! Thank you for serving

[@gustav_max]

fucking 10/10 amazing explanation thank u so much

[@ComputerScienceLessons]

Thanks :)KD

[@thexxmaster]

Thanks a lot

[@durreadanchouhdhary4587]

nice video Sir . But my question is .. if S=1, R=1 then what will be the value of Q(t+1) ... here are the options ... 1, 0, -1, invalid ... please answer this as soon as possible

[@PhinAI]

If both S and R = 1, both Q and not Q will go to 0. This isn't allowed, as it creates a race condition, which is when two digital gates race each other to change states, yielding an unpredictable output due to the outcome being dictated by the gate that reacts faster than the other.

[@markfinn825]

At 3 minutes and 21 seconds into this video how exactly does someone know that the top output is a 1? When what you need to know is that the top input of the set inputs OR gate is a one when bottom input of the reset OR gate needs to be know first to know that.

[@andrewwatts1997]

In real life, it's startup state is considdered random. Because any of the two states is determined by wich nor gate is stronger than the other to force a 1 on the output. It's why whenever a cpu starts up all registers need to be reset and put in a known state for it to function propperly. In the video he assumes the top one is set because it helps make the explination simpler.

[@ryanopitz846]

I have a similar question. How do you know that both of the inputs for the top gate are 0 when the second input of the top gate is dependent on the output of the bottom gate, which is in turn dependent on the output of the top gate? It seems paradoxical. Clearly I'm missing some unspoken rule on the ordering or just misunderstanding something?

[@ashenisuranga2915]

The starting state is determined at the moment the power suplied. its random Q can be either 1 or 0. but once its determined the the other become imedeately the opposite of that .

[@夏勝海]

Thank you for your interrogation I was so lost at that level

[@shivangikansal8025]

great explanation and I appreciate that a practical example was also included in the video which made it really easy to understand :)

[@ComputerScienceLessons]

Thanks for saying so - I appreciate the feedback

[@tensorbundle]

In my 12 years of engineering education, you are first professor who clearly and concisely explained the SR latch operation without causing any confusion. You are a genius. Thank you sooo much

[@ComputerScienceLessons]

You flatter me. Thank you. :)KD

[@gizmodobaggins7040]

@@ComputerScienceLessons The changing of colours like we are watching a super slow speed playback reallly really helps to understand what is happening, thanks!

[@lumerify]

12 years of engineering education and you're still learning about SR latch. Oof much?

[@andrewwatts1997]

Or a failure of education.

[@JokerLover123]

​@@lumerify He never said that. Read the comment again.

[@stevenmcg1986]

I am currently taking a digital fundamentals class for my computer degree and I have been struggling a lot with these chapters that are starting to cover latches and flip flops. I have a difficult time comprehending material simplify by reading out of the text book, and I've tried several videos on KZbin to help. None of them have worked; they have still been too confusing. Your channel has been a blessing so far. Very easy to understand on how slow you explain the information and the visuals are good. I'm going to continue watching them all and taking notes. Thank you!

[@ComputerScienceLessons]

That's great to hear. Thanks for the lovely feedback.

[@yuurishibuya4797]

That’s great to hear, shows you have not given up and you are trying to understand, learn by finding different ways. Small tip: You mentioned you had trouble understanding the concept by reading the prescribed text book right, now that you know this topic, go back and read the chapters covering this in the book. This time concentrate on how the author is trying to communicate this information in the book. Why his language constructs are difficult to understand, how you can break it out so that next time you can learn a difficult concept by reading a book written in a convoluted language.

[@essennagerry]

@Sundeep Kumar That's also my question... because in the very, very beginning there is no signal from anywhere, so do we regard that all as 0s everywhere? Then we get two 1s after both NOR gates which feed back to each other and their input becomes 0 and 1 for both, which then means their output is two 0s, which means makes their inputs once again all 0s, which makes their outputs two 1s again, etc, etc. Endless loop. Is a flip-flop in such an endless loop eithout any electricity and any input? I really need someone to define the beginning for me, how does it all start. If it starts with the S signal setting it, then all those 0s are valid input, so why aren't they valid before the S signal sets it? That's really confusing to me.

[@essennagerry]

@@yuurishibuya4797 That's a good tip! Another tip I would give is to try qnd imagine visually what the author is trying to say with words and try drawing it, maybe even draw it in panels just like the panels of a video explaining it.

[@luckypi7327]

BY FAR the best SR Latch and FlipFlop explanation video series on KZbin! Please keep making videos. Excellent

[@ComputerScienceLessons]

That's lovely to hear. Thanks a million.

[@russiachan2]

I didn't understand SR latches at all until I saw this. Thank you so much!

[@jdb2957]

Thank you! Thank you for you hard work, as a scientist and an educator! Thank you for putting the time into these videos! Thank you being British, as sometimes I forget I'm not watching a great BBC documentary! Thank you, Sensei! Thank you!

[@ComputerScienceLessons]

You are very welcome and you are very kind. Thank YOU :)KD

[@julianacarvalho4229]

I didn't understand what happens when q=0, because of the nand logic ports, should it be invalid when E=0?

[@ComputerScienceLessons]

Have you watched the second video in this series yet, The Gated SR latch? This is when I introduce E? :)KD

[@theidiotwithinternet]

This video is absolutely great

[@ComputerScienceLessons]

Thank you so much :)KD

[@shvideo1]

Great Educational video. Comprehensive and clear explanation. Thank you for taking the time and for the quality.

[@andrewgross8125]

Why do you assume the outputs for Q and Q complement at 3:16? Who's to say that Q has to be high? I don't understand why it's just assumed to be that way.

[@madhavvinod655]

yes

[@madhavvinod655]

why i dont get it

[@sarahbiebah]

the thing is: the output differs depending on whether we start by outputing S, then transferring its output to an input of the NOR gate with R or outputing R then transferring the output as an input with S. Like for the first SR Latch made of NOR gates, assuming S=0 and R=0 If we start with S=0, Q'=S=0 then (R+Q')'=(0+0)'=1 so Q=1 BUT if we start with R, it flips: R=0, Q=R=0 then (S+Q)' = (0+0)'=1 so Q'=1. Completely different answers. So, which is the dominant path here?

[@sarahbiebah]

or do we just treat the whole circuit as a single NOR gate, since S=0 and R=0, (S+R)'=Q, so Q=1 and in turn the inverse of Q will then be 0 ??

[@mikey.audio.]

You're absolutely right. This used to bother me because I overthink things. The way i see it, the answer is: race condition. Basically, both results are valid, as seen in the truth tables at 10:01 . You don't care whether Q or Q' is set. All you care about is the fact that they are opposite. After all, this is a Set Reset latch, so you can put it into a favorable default state if it initializes into an undesirable state. As long as R and S do not violate the one illegal condition for whichever latch, you will have a latch that initializes into one of two states, which can be adjusted by the inputs as needed. To answer your question explicitly, there is no dominant path. It all depends on the propagation delay of the components.

[@mayaanderson9021]

​@@mikey.audio. I overthink too. Thank you for your simple but effective answer. It clears my doubts and persuades me to deal with the question later when I learn more about the delay.

[@disara.dm07]

Good luck for your exam :)

[@7hotfuzz7]

My department head teaches Digital Logic Fundamentals and bless her heart she has tons of experience in the industry and has 2 PHDs. She's super nice and extremely helpful but she can't explain a concept concisely to save her life. This is an easy concept that was just presented very poorly to me. Thanks!

[@johnpro2847]

dynamic RAM uses another method as it is much cheaper, a capacitor and transistor (super small of course)

[@ComputerScienceLessons]

Indeed. What do you think of my DRAM videos? kzbin.info/www/bejne/f16ciYqqmbySedE :)KD

[@essennagerry]

But how does it START to take on values? Because in the very, very beginning there is no signal from anywhere, so do we regard that all as 0s everywhere? Then we get two 1s after both NOR gates which feed back to each other and their input becomes 0 and 1 for both, which then means their output is two 0s, which means makes their inputs once again all 0s, which makes their outputs two 1s again, etc, etc. Endless loop. Is a flip-flop in such an endless loop eithout any electricity and any input? I really need someone to define the beginning for me, how does it all start. If it starts with the S signal setting it, then all those 0s are valid input, so why aren't they valid before the S signal sets it? That's really confusing to me.

[@ComputerScienceLessons]

When the latch is first powered up, one of the logic gates will most probably come to life ever so slightly faster than the other, due to imperfections in the components and wiring and because of propagation delays caused by factors such as the ambient temperature. But there’s no way to know which one will come one first. Even if they come on at exactly the same time (and end up in what is called a metastable state), one will eventually tip the balance (due to imperfections, etc.). Once one of the gates is high enough, its output will turn the other off. The latch can then be initialised as required by setting S or R. :)KD

[@essennagerry]

@@ComputerScienceLessons Oh ok, so we can't actually know which is S and R? How do we know afterwards - can we at this stage determine Q as the one with output 1 and notQ as the one with output 0, and based on that determine that the input paralel to Q is S and the input paralel to notQ is S?

[@HealthFactoryOfficial]

you are a life saver, now I understand the concept. Other youtube channesls were going through a lot of what you said like we already knew. This is easy to understand for any beginnger

[@ComputerScienceLessons]

Delighted to help :)KD

[@hrishikeshkashyap3715]

Those who are confused, Q= House of 1 & Q°= House of 0. Therefore, if Q has a value of "1", the Latch stores 1. It's because Q is the House of 1. And, if Q° has a value of "1", the Latch stores 0. It's because Q° is the House of 0.

[@Jas_01101]

So when both the inputs are 0, is one NOR gate behaving as a 1 input NOR? Are both the initial inputs applied at exactly the same time?

[@ComputerScienceLessons]

Once the latch has reacted to a change of inputs, and has settled, one of the NOR gates will have both of ITS inputs the same. In this sense, the NOR gate is behaving like a one input NOR (which is essentially an inverter), but I'm not sure if that matters. Because of propagation delays in the wires of any circuit, it is highly unlikely that both inputs of the latch will change simultaneously (in fact if they do, it is briefly problematic). Simultaneous input changes are mentioned in a later video of this series :)KD

[@babafunmiseadebowale7746]

Thank you, the video really helped. My problem was how it could work if they both simultaneously need input from the other

[@ComputerScienceLessons]

You are welcome :)KD

[@beegdigit9811]

How does the electricity get captured between NOR and Q? Shouldn't it dissapate somehow as it looks likes the part between NOR and Q is storing electricity like some kind of battery? The truth table of NOR looks strange as well, how can you get voltage output out of no voltage inputs?

[@ComputerScienceLessons]

It's important to realize that a logic gate symbol is just an abstract diagram of a circuit containing several electronic components. I had a student once who struggled with the idea that if you put NOTHING into a NOT gate you get SOMETHING out. It became clear to her when she realised that all logic gates are connected to a power supply, but we tend to ignore that when describing their behaviour. :)KD

[@beegdigit9811]

@@ComputerScienceLessons Indeed, I jumped into this video without looking at what the logic gates are composed of themselves, thanks.

[@yusufkenanturak]

Finally excellent source for Logic Circuit, Thanks from Turkey.

[@ComputerScienceLessons]

You are most welcome :)KD

[@qE1QflvdOIVg91jmUUiL]

You're awesome please do one for jk flip flop. best video explanation ive seen

[@chriserony]

Are S and R interchangeable? How does the circuit determine which is which since its identical. Is it from where the power source is?

[@ComputerScienceLessons]

Because the circuit is symmetrical, they inputs are whatever you want them to be. As you suggested, which is which depends on how you choose to apply the input signals. :)KD

[@CookCraftandBeyond]

Really commendable job!!! Keep Rocking!!! Saw this video, and immediately subscribed!! I like the way you approached the topic. Great for beginners. Thanks a ton for this!!!

[@ComputerScienceLessons]

Thanks for the great comment. Still rocking. :) KD

[@alejandromedina4540]

Clear and concise, it shows just how well you know your stuff. Thank you so much

[@ComputerScienceLessons]

You are very kind. Thank you :)KD

[@wesdaaawg]

Very concise explanation. Great work sir, thank you!!!

[@longlostcoder6322]

Please!!!! Pretty PLEASE! make a few videos on DL latches, adders (w/ and without subtraction), multiplexers and uses, as well as decoders.

[@ComputerScienceLessons]

I wish I had the time. I really enjoyed making the electronics videos and would like to return to them one day.

[@mattiass4893]

I felt very sophisticated watching this tutorial

[@ComputerScienceLessons]

:)KD

[@isuckatthisgame]

Can we put complements on inputs (both S and R inputs) to make it 'active high' SR NAND latch?

[@dhrubajyotipaul8204]

You explain better than university professors. Thank you!

[@ComputerScienceLessons]

You are most welcome. Thanks for commenting :)KD

[@HoD999x]

at 3:28, why is the top nor already producing an output but the bottom one isn't? the setup is symetric, so both should be on instantly, then switch each other off and on again in an endless loop.

[@ComputerScienceLessons]

Propagation delays which depend on external conditions mean that it is highly unlikely both inputs will be set to low at the same time (and it's low voltage that represents 0, not no voltage). Nevertheless, the circuit will reach equilibrium as soon as a pulse is applied to just one of the inputs. :)KD

[@HoD999x]

@@ComputerScienceLessons so the starting state is random?

[@ichwanwiradarma8518]

RS Latch dari pintu NOR saling berkebalikan dengan RS Latch dari pintu NAND...., seperti pd S=0, R=0 dikatakan stabil utk pintu NOR yg berakibat pd output Q=0, Q'= 1atau Q=1, Q'=0. Set pada S=1, R=0 dan output Q=1, Q'=0. Reset pada S=0, R=1 dan output Q=0, Q'=1. Sebaliknya RS Latch dari pintu NAND, dikatakan stabil jika S=1, R=1. Set pada S=0, R=1 dan output Q=1, Q'=0. Reset pada S=1, R=0 dan output Q=0, Q'=1. Dan kondisi terlarang utk pintu (logika) NOR gate, jika S=1, R=1 yg berakibat Q=0,Q'=0. Tapi sebaliknya pada NAND gate, jika S=0, R=0 yg berakibat Q=1, Q'=1.

[@flybynjght2324]

Thank you so much for this explanation. Some electrical engineering students are are more confident now because of this video. I know I am

[@ComputerScienceLessons]

You are most welcome. Thanks for the comment :)KD

[@mandrewsvideos]

Thanks, this was very useful. I appreciate your explanation of the outputs being denoted as inverse and the explanation of the invalid state. This part gets glossed over in many other people's explanations (probably because they don't have a very deep understanding of the thing they are attempting to explain). Thanks again

[@davidmilman2850]

your videos are really good, and after discovering your channel, it's nearly impossible to go back and learn from other sources. When I discover a video on a particular subject that I need to learn for my degree, I immediately feel relieved and relaxed. So, I just wanted to say thank you for that and keep up the good work! However, if I may, I'd like to make a suggestion. Sometimes it's a bit difficult for me to navigate through your videos and know what precedes what. While everything is relatively organized in playlists, sometimes we learn topics that are integrated into other courses and then there is no match between "reality" and the order in which you present your playlist. This causes me to enter a video and then discover that I need prior knowledge in order to understand it, and then it's a bit difficult to find the preceding video. Therefore, if you could indicate in the description of each video the one that preceded it. Something along the lines of "If you haven't watched XXX yet, here is a link to watch". And so on.. In any case, thanks again and keep doing what you might do best in the world! All the best and happy life.

[@ivanchen3141]

so what will happen if S R both =1 and then turns to 0 simultaneously ?

[@ComputerScienceLessons]

A set or reset signal will sort it out. These things are initialised first. :)KD

[@yvesilboudo7009]

Thank you so much. I hated my digital logic class because of latches and flip flops.

[@folkertmuntz8719]

These video's are very good. You are helping me through Uni! Thanks!

[@ComputerScienceLessons]

I'm delighted to be of service. Thanks for commenting :)KD

[@emyl1999RO]

She: I like bad boys. Me: *Sets a SR Latch with 1 and 1.*

[@anirudhbhalekar]

*Wait that's illegal*

[@gracepeters2361]

Why out put q has to be 1 initially it can be q bar also this will give rise to egg and chicken problem

[@ComputerScienceLessons]

It is theoretically possible for a latch to remain in a so called 'metastable' state indefinitely. However, it will eventually settle because tiny imperfections in the components and wires result in current propagation delays. :)KD

[@gracepeters2361]

@@ComputerScienceLessons thanks for the reply and does it mean we can safely say that one input is reset or set with respect to other???

[@CatnamedMittens]

Might be the most confusing thing in history.

[@ComputerScienceLessons]

I think quantum computing has it beat. :)KD

[@CatnamedMittens]

@@ComputerScienceLessons I ended up getting it thankfully.

[@iloveblender8999]

Great! You saved a lot of my time.

[@maxximvigneau444]

This explanation is perfect! Better than my Digital circuits course that I pay $700 for

[@sharshabillian]

Found the reason that such pointless sites continue to exist LOL

[@dotcomwhiz]

The last comparison is wrong for the NAND gate SR latch. It shows high inputs and also high value for Q. It should be low value for Q.

[@daemiax]

Well, I have always considered the latches as some sort of electronic toggle switches. If the leaver is up the input is one, when the leaver is down, the input is the opposite. So it's like the electronic equivalent of a mechanical toggle switch