Does Using Guard Traces Really Reduce Crosstalk?

[@bertsimonovich7297]

Personally I do not use guard traces. In our DesignCon 2013 paper Eric Bogatin and I did an exhaustive study on guard traces. As part of that study we also showed that location of the grounding vias can have a profound on the effectiveness of the guard trace and in some cases made it as bad as having no guard traces. In the end, the key conclusions were; 1. In all high speed digital applications, where -50 dB cross talk is acceptable, there is never a need to implement a guard trace. This cross talk can be achieved in stripline traces by just increasing the spacing between aggressor and victim to fit a guard trace. 2. A guard trace, even “well shorted”, has minimal advantage. To fit the required shorting vias means spacing the aggressor and victim lines very far apart which by itself reduces the cross talk more. 3. Using a guard trace with microstrip offers high risk of incorrect termination with little potential reward and should never be done. 4. The optimum configuration for a guard trace is to use shorting vias on the ends, and match the length of the guard trace to the coupled region only. When used in stripline structures, such a guard trace can result in near end cross talk of less than 0.03%, which is -70dB isolation, compared with -50 dB isolation for the same two lines without the guard trace. Far end cross talk can be eliminated. 5. Any extension of the guard trace outside the coupling region, with shorting vias on the ends, will reduce the effectiveness of the guard trace due to the added length and finite inductance in the via. In one case studied, when the guard trace was just 100 mils longer at each end, the peak-peak amplitude of the near-end noise was just about the same peak magnitude of the no guard case. Because the details depend on the rise time and dimensions of the lines, a 3D simulation is the only way to quantify the actual benefit of a guard trace with vias in a practical situation. A link to an SI-journal article and link to full paper is here: www.signalintegrityjournal.com/articles/1341-guard-traces-love-them-or-leave-them

[@Zachariah-Peterson]

Thanks Bert for the link to the DesignCon paper, I pinned this comment, I also am not a guard trace user for multiple reasons.

[@thomasyunghans1876]

Hi Zach, I was disappointed that you didn't try to repeat Eric's experiment where he stated that you could create a resonance in the guard trace which could even increase the crosstalk if the guard trace wasn't handled properly. Did you try to repeat that?

[@Zachariah-Peterson]

The point about creating the resonant cavity with vias is something I'm saving for a different video on coplanar waveguides with ground. Aside from that, I think my other points are consistent with Eric's.

[@shuashuashua1]

Im using guard traces mostly for HV (rectifier mains 325VDC), when have to deal with single or double sided boards, its great to mitigate noise from switching, as addition to snubbers.

[@Zachariah-Peterson]

This is similar to bringing ground closer to the switching node, something which I discussed in another video.

[@big_whopper]

Why is the rule of thumb 3W related to trace width as opposed to the GND height? My intuition tells me trace width would relatively irrelevant

[@thomasyunghans1876]

Trace width and height above/below the return planes are both significant when determining controlled impedance traces and these are 50 ohm traces. I believe when people talk about the 3W rule they are referring to a guideline that is referring to crosstalk between 50 ohm lines. If the impedances were higher you would need something greater than 3W to achieve the same levels of crosstalk.

[@big_whopper]

@@thomasyunghans1876 oh! The 50 ohms already takes into account the ground height! Right?

[@thomasyunghans1876]

@@big_whopper That's right!

[@jeremyglover5541]

they are 2 sides of the same coin

[@Zachariah-Peterson]

​ @Caleb Crome Yes Thomas is correct, if you had a 50 Ohm trace you would have a fixed H value for a given W value. However, the W value needed to hit a crosstalk target for a fixed impedance is a nonlinear function of H, so as you bring H closer to the traces you can violate the 3W rule and bring your traces closer together.

[@godzich]

Hi Zacharias, Thanks for reacting to my feedback - much appreciated. I fully agree that it generates extra (and unnecessary) labor when you add guard traces manually. Additionally, placing high-speed traces at 3W (or even 4W...8W) distances gives you excellent results when it comes to crosstalk. Nevertheless, you would normally like to fill your plane layers with evenly spread copper. Flooding with copper those sparsely spaced high-speed signals add these "guard" traces automatically. You just need to ensure that you have vias distributed along the guard traces and not leave them floating - not to create resonators and make things worse - as Eric pointed out. The worst thing would be to leave guard traces floating but this mistake can be avoided easily by configuring the copper pour properly (leaving no islands). Avoiding unnecessary work (and drill holes) should be on everyone's agenda. Using guard traces (or fills) is a good option when you are striving to absolutely the smallest crosstalk, but is probably overkill if you can space your high-speed traces far enough. And as you said, it does not buy you more real estate on an already cramped PCB. Cheers, Christian

[@reynaldoloera8237]

Have you written a sort of Altium Designer User Guide on how to perform this kind of analysis (PI analysis, SI analysis, etc.)? I'd be really interested in it ! It would be a super step ahead vs EMCAD simulation tools that often spend a lot of time in this kind of tasks :). Thank you in advance !

[@Zachariah-Peterson]

I have not written a user guide on this, but I probably should compile the key articles on this topic into an ebook, and then make a video series out of it! This is a good idea because there are a lot of steps involved and I think the information is scattered around too much.

[@chromatec-video]

Eric simulation shows an increase in crosstalk but Simbeor shows a decrease in crosstalk - neither uses stitching vias - so which one is correct?

[@Zachariah-Peterson]

In Eric's presentation he shows that improperly spaced stitching vias create a resonant cavity that increases crosstalk. In another case, he shows a slight decrease starting from a very low value. Simbeor shows a much larger decrease using the extracted linear network model, I did not do a full wave simulation in the interest of time so maybe the results will be different.

[@petersage5157]

Many EEs make a distinction between grounded traces and guard traces tied to the receiver's reference voltage, which may be different from system ground. For example, a single ended analog front end with the receiver biased between Vcc and ground. This seems to be where I've seen guard traces most frequently used in metrology grade equipment that EEVblog has featured in teardown videos. Still not sure how this is supposed to work unless it's meant to be parasitic LC between the receiver and the signal trace.

[@big_whopper]

Guard rings are for picking up stray/leakage currents, right? I guess it’s for resistive coupling as opposed to reactive coupling.

[@jeremyglover5541]

@@big_whopper yes, where i've seen it (guard ring) most, is protecting high impedance feedback nodes from leakage currents (LC) in low noise references in linear, or mixed signal application. Same/similar reason you would make sure to clean the PCB very well.

[@InTimeTraveller]

​@@big_whopper how can it be resistive coupling? If the guard traces was resistively connected to the victim trace then it would be part of the same trace, not a guard one. I think that all guard traces are by definition reactively coupled.

[@big_whopper]

@@InTimeTraveller I was thinking of super high impedance designs, where any surface contamination can cause leakage currents across the surface. The guard ring can help slurp up those stray currents. Definitely not my specialty though

[@zyeborm]

@@big_whopperyeah that's how they are used, the big thing is the trace itself is (often) exposed through the solder mask so if there's some flux or a fingerprint (or just leakage through the board for sensitive things) on the board the guard ring is there to take the current. By driving the guard ring voltage to be close to the signal voltage the current across that resistive connection is minimised. Also if they are doing metroligy grade work they will probably care about getting a few millivolts less noise from the regular guard trace use.

[@RedRacconKing]

Thanks Zach, this was very informative.

[@MrThoriam]

Can you prepare simulation and compare it with real measurement?

[@Zachariah-Peterson]

I would need to make a test board, maybe I'll do that!

[@TheGenoharadan]

In 6:25 when he starts routing, we can see the clearance aroung existing traces. Where can I set this option?

[@Zachariah-Peterson]

To make the clearances visible, you need to go into the Preferences dialog. Look in the PCB Editor --> Interactive Routing section, and there will be an option to display the clearance boundaries while routing.

[@arijitdas1884]

Hi Zach, Thanks for the video. So what I understand, we need to be cautious about the vias spacing in a grounded guard trace when we are particularly dealing with digital signals. But if we are dealing with analog or RF signals, is their any limitations we need to be wary about for placing guard traces with stitched ground vias, other than the fact that the via spacings should be corresponding to lambda/10 or lambda/20 of a much higher, far-away-from-our-operating-band frequency? In RF boards I have worked on, I have seen such guard traces almost everywhere, especially between Analog front end IC pinouts/RFSOC fanouts, so gaps between device pins are already fixed. Here I would like to ask another question - given the expected power of the signal propagating in the agressor trace known, how to concluded what should be our target crosstalk/isolation requirement? I have also simulated such arrangements in different simulation softwares, and to my surprise, different isolation values came up (S parameter analysis) in different softwares (3D FEM simulators used in all of them). That's a different confusion altogether faced regarding this isolation checking..😅. Anyways, without testing, could not verify which one is correct.

[@Zachariah-Peterson]

I can say that if you are doing this with very tightly spaced vias you are basically making something that should function like a coplanar waveguide. The span of the pour that makes up a coplanar waveguide also affects the isolation just by increasing the distance as well as setting the boundary condition for the electric field in a quasi-TEM analysis. A thin guard trace with a bunch of vias along the trace is basically like a very thin section of pour, kind of like what Eric showed in his presentation. The presentation from Eric just telegraphs the same ideas in guard traces onto thin copper pour so his conclusions are valid in both cases. In the RF devices I have done I have never intentionally used guard traces, but sometimes the way pour appears on coplanar lines, it looks a lot like a guard trace. This is definitely the case on radar boards where the lines need to come in/out of a transceiver in parallel. As far as isolation/crosstalk requirement in RF signals, there is no specific or required value for every system. Typically you have an SNR target that you need to hit as measured at the I/O on some transceiver. You can actually determine the minimum SNR target if you like from information in the datasheet, the minimum input power given on an interconnect typically is determined from a test condition with specific noise within the component’s receive/transmit bandwidth.

[@Zachariah-Peterson]

And about the differences in simulators, there is always some kind of discrepancy that usually results from meshing. There can also be differences resulting from the frequency scan range and discretization, as well as any interpolation that might be applied to the simulation results. I'll assume that the boundary conditions were consistent in your simulations!

[@qwery717]

Yes 3W works, however it almost impossible to follow this rule with complicate which includes large FPGA/CPU and number of DDRs. The only way is to use microvia (and another issue that large FPGA/CPU packages are not designed for thruhole routing).

[@Zachariah-Peterson]

That’s true you cannot always follow the 3W rule in space-constrained situations, and the fanout into/out of a BGA is always problematic when the pitch is very fine, but in those cases you usually have a thinner layer anyways because you need it for those microvias. When you have the ground plane much closer to the traces you can violate the 3W rule and still hit an impedance target. I actually show something similar regarding the impedance deviation created by copper pour in my seminar lectures, and I showed something similar in another video. The same idea applies to crosstalk, as you bring the ground plane closer you can push traces closer together and you can get less of a crosstalk penalty than you would see in thicker layers.

[@qwery717]

@@Zachariah-Peterson Copper pouring easily becomes coplanar routing which complicates stackup calculation and if you don't pay attention can cause to impedance discontinuity .

[@jeremyglover5541]

Hmmm, I mean, I really appreciate Eric's experience and what he says is not untrue, but I do find that often his arguments for not doing something that does present a small improvement, are often biased by the areas he does his work. 1. they are obviously heavily weighed in by someone who doesnt work in analogue, or low noise mixed signal very much ... the improvements he calls meaningless, are almost always 0.X%. that isnt meaningless when trying to keep noise below 0.00XX%. 2. his arguments for not doing them are often justified by negative outcomes that could happen if you screw it up and in this case, make crosstalk worse, by leaving floating copper... I’m pretty sure anyone going to the trouble of routing guard traces today, isnt going to leave it floating.

[@Zachariah-Peterson]

I would agree with your point that he is talking to a certain subset of designers. Also his point about what happens if you screw it up, while a valid result, is not the whole story, that's why he looked closer at pour (which is basically just a wider guard trace). I will admit I am also speaking to a certain subset of designers because this technique is often brought up as a way to address crosstalk between digital nets, not necessarily precision analog where you need muuuuuch lower noise and every X% reduction counts as a benefit. So yes I agree with you this is mostly addressing the digital designer who needs to route a lot of traces and is worried about signal integrity with respsect to dense routing.

[@jeremyglover5541]

@@Zachariah-Peterson oh sure. Funnily though, i actually agree with his point about pours. To some extent. They are well overused by beginners and sometimes just unthinkingly used, as a sort of fix all. People will do half the routing job and then just hit the fill button. It can lead to taking your eye off the ball so to speak and not visualising the loop area. I do a lot of polygon routing for dc regulators and i have to keep reminding myself to use only the trace that is required. Polygon routing is so pretty, so its easy to get carried away and forget about noise pickup from high z nodes and instability depending on bandwidth. Often times you are better served to create localised fills. Copper puddles. Especially if you have the luxury of a close reference plane. I have watched that whole video another day too and found it a mix of useful and frustrating. I think the main takeaway is use the tool for the job. There is absolutely good reasons to use copper fill and one that is not minor is copper balance/manufacturability. I need to remember exactly what was covered in that video. I think i remember shouting something at the screen about the usefulness of plane cap … lol. The best answer in lots of cases is of course ‘it depends’

[@Zachariah-Peterson]

​ @Jeremy Glover You're absolutely right about pours, when we had Eric on the podcast I made the point that if you're relying on pour to solve noise problems, then there is probably some other more fundamental problem that is creating the noise in the first place and you should probably address that first. Whenever I've done them in some of the videos I try to give the justification.

[@bertsimonovich7297]

@@jeremyglover5541 I agree with you. Gnd pours has the same spacing rules as crosstalk spacing rules, but you still need to pay attention as you have said.

[@bertsimonovich7297]

@@Zachariah-Peterson Many people use ground pours as a means to achieve copper balance on a layer. If you are a fan of the late Henry Ott, he advocated to not leave any floating copper on your PCB since there ia no means to drain any higher voltage charges that could build up. Many board shops will add copper thieving pads for copper balance without you knowing, which can be as dangerous as adding copper pour yourself. At least by doing it yourself with the right spacing rules, you control the design.

[@dmitry.shpakov]

Thanks Zach!

[@vladlv2]

This clearly contradicrs to bogatin results. In frequency domain is no resonance. Either tooling is different or bogatin point is wrong.

[@Zachariah-Peterson]

No they are not contradictory, Eric showed that when you ground the pour you can get lower crosstalk, however if stitching vias are used and you space them improperly you can get an increase in crosstalk. We just looked at a grounded trace, which is equivalent to thin copper pour. The point we are both making is that in order to even place a guard trace or pour with stitching vias, you have to space out the traces far enough to already meet or exceed 3W spacing, so you will have low crosstalk anyways. Even his order of magnitude peak crosstalk value was similar to the Simbeor result.

[@vladlv2]

@@Zachariah-Peterson you spaced vias as improper as could and still has no resonance on graphs. Point he was making there could be standing waves between vias if they are not spaced close enough. and this could create boost in crosstalk, however this is not observed here, graph has no clear resonance and look exactly like without pour. maybe frequencies he was talking about are 10GHZ:) no idea) however i think simply this tool is not modelling completely all aspects. Probaby simulation in ADS could be done for that.

[@Zachariah-Peterson]

@@vladlv2 3D simulation would capture everything. The spacing on the vias I used just corresponds to the ends of the guard trace connection, that was intentional and was not trying to replicate that particular result from Eric, I just wanted to focus on the guard trace itself. Those vias are cylindrical scatterers, the region where the resonance would occur in my model would be very weak because the radiation scattered from those vias is inversely proportional to the distance from the via, so you most likely will not see it at these large istances. It's much clearer when you look at more closely spaced vias due to the 1/r falloff in electric field intensity.

[@ledricelektronika6635]

Amazing

[@rafalzasada8826]

Well, so it look like I don't have to worry about guard traces fot the rest of my life :)

[@Zachariah-Peterson]

Yeah there is no point in them, there are other methods that are better for reducing crosstalk.