Do You Really Need Power Planes? Are you sure? | Eric Bogatin

[@carlosgarcialalicata]

This is absolutely PRICELESS!! Great ideas, with clear explanations, scientific theory with proven experiments... in one talk, breaking internet myths

[@remy-]

Almost two weeks of holiday passed; finished Min Zhangs EMI course, begun Phil Salamons course via Fedevel and now watching you two: a golden duo. My holiday couldn’t be better! Fields are awesome 😀😀 Your channel keeps being interesting, thx!!

[@RobertFeranec]

Thank you very much Remy

[@SagaD888]

I never get this much visualisation in my 12 years of industrial career Its great interaction Thanks lott Robert and great Eric sir

[@BRUXXUS]

I just meant to open this tab to watch later, and suddenly realized that I had already watched 20 minutes! I'm so happy that KZbin recommended your channel to me! I can't wait to continue watching this video, then go onto more!

[@skmgeek]

have you finished watching the video yet?

[@forresterickson6225]

Regarding copper pour. I used it because I was told it reduced waste in the PCB fabrication process (less copper sulfate perhaps). I use a (mostly very) solid ground plane as signal return and try to cover any gaps in the ground plane with copper on another layer stitched with vias. Give the current paths the smallest diameter circle in which to circulate and the current will take it which is a win for all. My experience is with two layer PCBs and I make the bottom side ground and keep the routing to the top layer. Use a capacitor to ground on EVERY signal that leaves the PCB right at the connectors to limit the bandwidth of the signals to no more than is necessary for the job at hand.

[@Stewi1014]

Absolutely love Eric, such brilliant understanding of the issues he's teaching us to solve. So much to take in... I'll be re-watching different parts in the future for sure.

[@gsuberland]

Quite a few important revelations in this video! Particularly enjoyed the explanation of using capacitors between planes of different voltages as a form of "DC blocking via" for return currents - I had seen this done before on boards with split planes and never understood the purpose.

[@dario_fresu]

- 14:00 important point to grasp regarding using other planes for the return current - 35:00 super important discussion regarding Stitching Vias and cavities

[@jeff-oi7cl]

such a treat with you Robert and your guests!

[@codedesigns9284]

Mind blowing! We learned a lot from this. Thank you Robert and Eric. I can’t say we understood everything perfectly, but it clarified many of the questions regarding resonance! I would love to see some practical boards that you have created where you would make changes armed with this valuable knowledge. Excellent video and call!

[@bit0fun]

This is great; I've been going on an exploratory part with signal integrity simulations with openEMS and then saw this video pop up today Thanks a ton for this interview!

[@TheOleHermit]

Got my layout & signal tracks on a 4 layer PCB in Kicad. Was planning S+G+P+S, with ground pours isolating the signal tracks on layers 1 & 4. NOT! Saw this video before proceeding. Thanks for setting me straight, just in time. Eric is a great instructor and you ask the right questions. Great series. 👍

[@jonnymakers9560]

In Cadence / Allegro you can create a power plane and still route nets etc. Altium a power plane does NOT allow nets - but you can divide power planes. It is usless. Always choose a normal layer when using Altium. They need to fix that. But they wont!

[@Kefford666]

It can be convenient to use layer 3 for power. When you have a bunch of components all needing the same voltage it's nice to be able to just drop vias. You just need to route as much as possible on layer 1. The last PCB I made I put all comms and important traces on layer 1 only and the only traces that go between layer 1 and 4 are slow signals e.g. an enable line, an LED.

[@ThePetaaaaa]

You can as easily use layer 4 for power. Just slap a polygon or two on there. A few short signal traces in your power polygon don’t do much - imho.

[@Kefford666]

@@ThePetaaaaa Yes that’s a good call, I might do that for the next version. The vias go all the way through too, no blind or buried vias.

[@jimjjewett]

@@ThePetaaaaa Are you suggesting a stackup of (S, G, S, P) instead of (S, G, P, S)? Isn't there also some problem with signals being between the power and ground? Also with this creating stubs from the connection on 3 to the now unconnected 4? I suppose these may all be minor, particularly for slow (relatively constant) signals, but ... isn't the return path problem also minor for that sort of signal?

[@ThePetaaaaa]

@@jimjjewett Yes (S, G, S, G/P). To my understanding both signal layers have the same ground plane next to them, so no no "return vias" required. However, the distance to the GND layer will be different. To my understanding layer 3-4 stubs won't be a problem until you go to GHz or above. As usual, it depends what your goals are. Primarily use S, G, S, G for capacitive sensing since I can shield the traces on layer 3.

[@AlbertRei3424]

@@ThePetaaaaa No one put power on an an external layer because you are radiating a lot

[@manishkumar-hr8fb]

Thanks Robert for this discussion with Eric. Till now I knew that we can use power plane as a return plane with same voltage as signal.

[@AbdullahKahramanPhD]

Back in my time, when I was a "learning engineer", Robert was not on KZbin.. Learning engineers out there, you are very lucky! Thank you Robert :)

[@RobertFeranec]

Thank you Abdullah PS: I also wish I had access to this kind of videos when I was learning hw design.

[@JanoyCresva66]

back in your time you had 1MHz signals so you did not have to worry about all this

[@AbdullahKahramanPhD]

@@JanoyCresva66 well, yeah, no.. I am 32.. Rise times on your everyday microcontrollers were almost the same as todays

[@chromatec-video]

Thank-you Robert for hosting Eric - these are always interesting. Personally, I would just use 6 layers. Also - copper pour is better for the environment!

[@jimjjewett]

How is copper pour better for the environment? Because you use less etchant? Because your signal is in an environment with more metal shielding?

[@andymouse]

@@jimjjewett Less etchant.

[@chromatec-video]

Yes - I prefer to leave copper wherever possible. This reduces the possibility of over-etching fine traces and I think it reduces warping during assembly if left on all layers.

[@andymouse]

@@chromatec-video Indeed.

[@heyrim72]

Thanks for the video. The thing where I learned to do a copper fill was actually when self etching pcbs. If you do a copper fill you can use your acid more often, it is faster and the resulting quality is better. Not sure if there have been some commercial manufacturing reasons in the past, but today I would say this is a non issue. For commercial products usually emc is the most important part anyway.

[@Konecny_M]

It matters when you want consistent electrodeposited copper thickness.

[@weeeeehhhhh]

@@Konecny_M Copper balancing. It is good practice and recommended (but not necessary always) to have an equal amount of copper on both sides of a PCB. This allows for an even distribution of copper when the manufacturer is plating up the outer layers. Also helps maintain via integrity, especially if you have requirements that vias must have a minimum wall plating.

[@Helena-gp8bn]

This is a so-valuable video, thanks a lot Robert and Eric.

[@eyallampel]

Thank you Robert! , in all of your videos you always focus on 4 layer stackups, I wish you will make a video on the best 6 layer stackups.

[@tradegrabber4854]

Awesome lesson, thanks Robert and Eric.

[@EDGARDOUX1701]

Great Video Robert...the BEST channel on KZbin.

[@RobertFeranec]

Thank you very much Edgar

[@nabilel-sheikh9747]

what i understood from the last couple of minutes in the video , it is not necessary to fill the top layer with copper pour and connect it to ground on bottom layer "in a double layer board" , this means we just do the majority of routing on the top layer and use only one solid continuous ground plan on the bottom layer , and that it is !

[@cornevanzyl5880]

Thank you

[@mievotechnologiespvt.ltd.1175]

Tremendous explanation and presentation

[@andychess]

Great video! Thank you both for giving up your time to make such in depth content, it is really appreciated.

[@DavidMcCurley]

This changes my approach to power planes. Thank you.

[@m.e.5018]

Excellent! Fantastic Material covered. Thank you Robert for making this available.

[@Jeremy-fl2xt]

Great content, and very interesting perspectives on the asymmetric stackups. I totally agree that the return path needs to be considered at the same time as signal routing, but sometimes it's possible to eek out a bit more ground with flooding. Using a CPWG to shield a signal (especially RF) from other signals can be critical for many designs. Also, designing for measurement requires making a "good" reference signal available along with the signal. "Ground" is usually the best - especially for single-ended probes like most scope probes, so a flood of ground connected to a solid plane can make high-quality measurement easier, but that does depend on good engineering of the ground.

[@mohammad.htarokh2891]

Fantastic video! If you read a book on EMC your idea about PCB design will change dramatically. Grounding is an important and less understood and often overlooked concept of PCB design. As a rule of thumb remember that for a PCB especially clocked digital(over 100KHz) ones, proper grounding is a must and you need to think of it right from the beginning! Either you need a ground plane or at least the old-fashioned ground grid.

[@schmetterling4477]

You always need to think about proper grounding, even at DC.

[@Christe4N]

Thanks, Robert, that was very interesting. Eric answered a question I have had for a long time. Thank you!

[@tubestar1979]

Very informative. Thanks guys !

[@mohd.farizulazman8594]

Learn a lot from this video.. Thanks to both of you.

[@JohnSmith-iu8cj]

What I didn’t understand at the end, if I have a solid ground plane on a 2-layer board, will a copper fill on the signal layer create problems or not? My understanding is that it’s better to have a copper fill and a solid ground plane with stitching vias because of the reduced inductance on the signal layer for decoupling capacitors and components and also smaller fields.

[@Retinatronics]

This is a great video. Please bring more videos with Eric.

[@romancharak3675]

Thank you, Eric and Robert! Fascinating stuff.

[@bernard.tomasevic]

I think Eric Bogatin needs to release a Fedevel course :)

[@seyyedmohammadsaadatmand5517]

Why in 59:12, the custom-made Arduino has two crystals but Arduino has two of them. And Eric told with exactly same component and the difference is only the layout. Also, the electrolytic capacitors have been removed. Also, I see a FB (Ferrite bead) but I don't know how they've used it. Since there is no capacitor after it to filter anything!

[@MaxWattage]

Great video, with lots of helpful insights and new ways of thinking about the issues.

[@sailtogether3236]

Прекрасная беседа! Спасибо!

[@supernova86]

While this was a great video... there are a lot of questions that arise from this. Also, many of his examples seemed to be very specific and unique instances, rather than comparing his way vs generally accepted practices in the design field. For instance - who the hell has just a floating plane in the middle of their stack-up connected to nothing? Literally no one.... That power plane is connected to the ground plane through capacitors at just about every IC. His first example would have been significantly more enlightening if Eric had used a board configured like his, against a board with 2 ground planes connected through vias. In his last example, I wished he would have also had a 3rd example of micro board to test against. The exact same ones his students designed, but with also a ground flood on top layer around the signal traces. If having a ground flood on your signal layer does nothing (even with a ground plane directly under the signal layer).... SHOW THAT IN YOUR EXAMPLE. He's comparing apples to oranges here. Let's make it apples to apples, please

[@xxportalxx.]

I think he actually answers most of your questions while discussing the theory at around 29 mins in. Basically what he's claiming is any signal via becomes an antenna, parallel planes form a waveguide that helps couple this to all of your other signal vias, which is where the noise comes from in this case. By making your planes the same potential, by bonding with vias, that waveguide effect is reduced. Your bypass caps at your chips will help, but he points out they're a lot less effective than making the planes the same potential. He also points out this isn't always a problem in all scenarios (I'd say you're mostly going to have issues at low signal strength and high frequencies, especially if you have a mix of high and low strength signals, for instance if you had low amplitude analog inputs and high amplitude digital outputs).

[@greghjelstrom2553]

I'm interested in the webinar Eric Bogatin mentioned about measuring signals with a scope. I went to the web page mentioned in this video (around 52:00) but I haven't found this subject. Great video by the way, I'm learning a lot! Thanks!

[@andbotelho]

Great explanations, thanks

[@PHamster]

I wonder what's the difference between the flooding: Rick's Stackup with Flooding (Granted with Power on the Outer Layers) kzbin.info/www/bejne/a2PJqaiIfM6Zgrc Eric's Suggestion of Not to Flood. Were the flood not stitched to the correct reference plane? kzbin.info/www/bejne/oZWme6uah5x_las

[@boonlau4171]

@54:47 High impedance probe definitely not enough bandwidth to handle a signal with 1ns rise time.

[@ricolauersdorf687]

Once i did some tests for a sensordesign where the old design was passive with coaxial cable and i wanted to power an amlifier near the sensor element. To stay with the old reception system, i decided a triaxial cable. The cables outside conductor was forced to be the metallics enclosure voltage, so i decided it to be gnd. I later then decoupled the outside gnd to hf cause of course it collects charge and so noise from the outside especially the gnd was "not allowed to" recepted from the sensor, without ferrite in series with litthe resistors and then a cap to V+. So the inner ring conductor on cable had to be the positive supply voltage. since the inner ring conductor is more near to the signal, it has high coupling to the signal on the wire. So the whole amplifier module and the sensor was not ac reference-coupled to gnd, but instead to V+. on the reception, it was then coupled to gnd. i used a lot capacitors for the coupling. I had a V+ plane instead of a gnd plane in the sensor. the signal was as never seen before and as i like to do, i tested all circumstances with a "high frequency massage device" from "esoteric" store, to emmit outside noise to test for the best emc circumstances. Later then, i changed the dc level on the signalwire (signal only of ac interest) to the suply level, sourrounding it. This then lead to no more recognizeable "microphonic effect" anymore. of course the sensor now has a little metallic enclosure, on ac- decoupled gnd from the systems perspective, so something which can lead to an "antifaradayic cage", so i believe. So i routed the signal always nearest to V+ and away from enclosure. I learned a lot during the project, parallel watching your great videos!

[@toddblackmon]

Interesting video, although it seems that Eric's argument may be more nuanced than just to not use ground fills. It seems rather to be "Ground fills aren't a substitute for properly managed return currents." For example, let's say you manage your return currents as proposed. It doesn't seem like there would be issues with stitched ground fills on the signal layer. For example you might do this for non-electrical reasons. Thermal comes to mind, perhaps mechanical in some cases, or even for improving the results of self-etched boards. (It seems a lot of other people here had similar comments.) Also, it would have been interesting to compare the board with the vias with the non-via board with caps installed.

[@leeslevin7602]

Fantastic discussion 👏 thank you both for a brilliant video.

[@lsfornells]

These videos are excellent, however as a suggestion I would edit them to translate imperial units when used by the speaker and provide a conversion caption to international. In this video the interviewed guy talks about "feet" and "square feet" as if nothing, as he doesn't seem aware (or care) that most people won't understand that (09:30). I would say that even Robert looks a bit perplexed at that particular moment, as he probably doesn't know the conversion right out of his mind.

[@daltonkraft4241]

Professor Bogatin is amazing

[@Konecny_M]

Power plane referenced to the signal driver positive rail will of course behave better than floating different rail plane - the source of the signal has low impedance tie to that reference plane. The problem of transitioning to different layers remains, but it is not correct to say the voltage domain is irrelevant.

[@erikmjelde4428]

This is great information that I will use!

[@manishkumar-hr8fb]

Robert, Pls make video on Cavity Resonance and how to suppress these on PCB

[@ttschabos]

Hi Robert, I see, that there is no ground pour on the top and bottom layer in all the experiments. If you have a power plane but also ground pour on top and bottom, the return current should have way less inductance when used a GND via next to each signal via, since the return current can change from the power plane to layer 4 (small gap) and then take the via path to the ground plane. This way, there should be maybe only 1.2x the inductance than when two ground planes would be use. What do you think about that?

[@wojtekgomboc]

thank you very much for very interesting video.

[@優さん-n7m]

@29:00, ok so if I use low ESL capacitor to connect the two plans that have different voltages using vias, how do I know if it is good enough? How can I run simulation? Also, for 4 layer board, the dielectric is between layer 2 and 3 and is quite massive unlike the prereg. This means that using layer 2 and 3 as GND and PWR is a very bad idea.

[@maheshpalika8985]

1. How to select the PCB materials 2. what are the things we have to consider before choosing the materials 3. Is there any separate way of materials selection for military, aerospace, and medical domains other than the highspeed domain?

[@weeeeehhhhh]

Mechanical stability, thermal expansion, rigidity/flexibility, thermal conductivity, thickness, cost are all factors in material selection. In other domains you would factor in coatings, cleaning and designing for environments of extreme vibration, heat, pressure, steam, vacuum

[@CppExpedition]

Wonderful talk 🎉!

[@bprud6443]

As an electronics repair technician, I'll add one reason why burying a power plane inside your PCB is a bad thing : it makes it almost impossible to find the source of a short circuit on one of the power rails.

[@Dinghly]

Priceless

[@giannisasp1208]

Thanks Robert! great information as always!

[@RobertFeranec]

Thank you very much

[@MohammadShikha]

So the power plane can act as a return path at any voltage so long as the path isn't split. Would this still hold true if it was power from a switching power supply?

[@losaminos59]

@32:20 how did Eric come up with the resonant frequency of ~2.5 Ghz for a board of 25~30mm? That's a quarter of a wavelength, but I thought generally, people are using half a wavelength for intuition of resonance and such.

[@andel0792]

Great video again! I watched this right after the one you made with Richard Hartley. I see you asked Eric several times wether the voltage on the power plane matters, but he kept saying no. On the other hand, Richard told you that when using a power plane as a reference, voltage does matter and it has to be the same voltage of the signal that is routed on top of it. I think there is some confusion here. I agree with Eric when he says that the voltage level doesn't matter for the propagation of the signal but when the signal gets to its destination IC, the field will spread, as Richard said. And this is why you should never reference a signal to a power plane whose voltage is different from the voltage that generated the signal. What do you think?

[@kushlavr]

Thanks! Very interesting topic! I learn so many from your videos. I feel like just finish a cource in univercity :-)

[@優さん-n7m]

Could someone explain the difference between the two boards at 58:00? And what does a "short cross under" mean?

[@BeMuslimOnly]

It was mind blowing. ❤️

[@kennyrebbe]

How about ground fill on multi-layer pcb's which have 8-14 layers? If I have solid copper gnd reference layers to signal layers, does it really hurt to fill on top or bottom with gnd? I typically pour on top and bottom for thermal reasons. If a signal has a proper signal return path, does gnd adjacent with a fill really have a bad effect? I would like to see higher layer count stack-up examples!

[@jungukko1146]

I am confusing too. He said we need return via with adjacent signal via, then we need gnd copper near the signal via. How can we add return via on gnd without copper pouring

[@vadimp4506]

Amazing, priceless knowledge.

[@Janamejaya.Channegowda]

Thank you for sharing.

[@habs6398]

I'm a little confused in terminologies here. What is the difference between a copper pour and a copper plane? In Altium, for example, you can have power/ground planes with negative connotation or alternatively copper pours with positive connotation. As per my understanding, both are essentially large copper areas at the end of fabrication, isn't ?? So, if we have a solid copper pour on bottom layer, as shown by Eric in this example towards the end of the video, shouldn't it behave exactly the same as a solid ground plane at the bottom layer (assuming everything else to be identical, of course)??

[@josesaumell2908]

I guess the main idea is to not use 10 degree C temp increase in your calculations. Playing with the digikey ipc2221 calculator, to get 6 mil trace (100mm long) for 1A in 1oz copper we must let the temperature rise be 30 degrees celsius for external layers. With that much small surface area I guess you wouldn't be able to feel any heat to touch.

[@ThePyrosirys]

I find that using a power plane makes routing so much easier in 4 layer boards. The likelyhood of having a signal going over a return plane discontinuity is much lower. I would wonder what the end result is with regards to actual noise in a real design

[@pkuula]

This video was eye opening to me. Im designing USB powered board with 8bit atmel uC and i was worried about power distribution! Board contains only a uC, NE555 and couple of slow optocouplers and signals only a few milliAmps here and there. 😀 Your videos are one of the best contents on its on area. Greetings from Finlad!

[@norm1124]

Merci Robert for the amazing videos. The better a video on KZbin, the less views it gets ;-)

[@rocket6786]

I still don't fully understand the core message. For the last example they used a 2 layer board and the regular arduino failed because it does not have a solid uninterrupted return path layer. But for 4 layer boards I usually go for the (Sig/Gnd>Gnd>Power>Sig/Gnd) and stitch them all with vias. This allows me to conveniently take a power via wherever I want instead of having to route a long power trace. One other thing is that the ground layer coupled next to signal layer should also provide a return path. I have not seen anyone mention this type of stackup. Also, it will be interesting to try the (Sig/Power>Gnd>Gnd> Sig/Power stackup)

[@squilly1974]

This is exactly what I do. Use the four layer (SIG/GND/PWR/SIG) and don’t route anything on the GND layer. Then all power is sunk to the power plain using a via. This is great for decoupling caps as I get a via to supply the cap then the cap to supply the IC. I also ensure that I flood the top and bottom layers with a GND flooding and then stitch the whole load together with vias, as I believe that this capacitively coupled the signal lines to ground giving a better GND return path. However this was not alluded to on the video so am I wrong 🤷‍♂️

[@rjordans]

@@squilly1974 if I understand correctly, the tricky part is when you have a signal that jumps from later 1 to 4. The reference plane for the return path will switch from ground to power at that jump. For fast signals, if you want to avoid EMI problems you may want to include a decoupling cap next to the signal via to couple the planes and give an easy route to the return signal.

[@squilly1974]

@@rjordans this is where I thought GND flooding came in. Not entirely sure if this is the case though?

[@rjordans]

@@squilly1974 Robert's asking the question around 25:50 ;-)

[@zerpharet]

It is said again and again that their should no GND pour on the outer layers. But all the layout datasheets I find for chip antenna or pcb antenna layouts show that ground pour. Is it because they just assume there is one, or do they really need them? I mean the GND plane is mostly part of the antenna.

[@fnumohammadkhajanadeemuddi250]

I have one, I am using a voltage converter 12vdc to 5vdc on a 4-layer board, two signals, 1 power, and 1 gnd plane. I can not just put the output of the DC 3.3 to the Power plan, In this situation, can I use the copper plane only to a certain extent?

[@paulgallagher2937]

Really great video. I've seen a few now. I'm in the process of redesigning a couple of our PCBs. I'm going to try the 2 center ground plane strategy and see if it fixes a couple of minor issues.

[@hightechsystem_]

I would like to see a proper stack up and strategy where power plane is necessary.

[@yasirshahzad3732]

can we get schematic or pcb layout of victim line board? as it is really difficult to understand

[@agr00m]

What about sensitive nets that route over a power plane split, but with an adjacent ground plane. For example, here's a typical 6-layer stackup we have and the sensitive net routed on layer 3 (inner signal). If routing on external layers is not an option, would stitching capacitors be advised? 1 Signal/Power 2 Ground 3 Inner Signal 4 Power 5 Ground 6 Signal/Power

[@yadisoloblack]

i would be interested to see a 3rd comparison of the noise influence on the victim line when you put in decoupling capacitors on the 'no return vias' board

[@pochuanpeng1729]

10 mils or 20 mils for 3A current, do we need to worry about dc drop ?

[@abolfazlomidvar47]

Great video, thanks. I have a question. In Sig/Gnd/pwr/sig stack up when top and bottom layers are ground poured and wherever changing layers occur, If I use ground via (i.e. connecting ground pours on top and bottom layers) close to signal via, wouldn't that reduce via resonance?

[@stefanosavio7151]

Which software have you used for 3d simulations at 12.14? Ansys? I'm trying ti obtaio na similar result but I'm not able to

[@NathanSweet]

Signal layers on the outside radiate more. Why is SGGS better than GSSG? With GSSG, what happens when we via from S to S? The return path needs to switch from one G to the other. Does that have potential issues?

[@nickbolton9435]

I'm not sure if this was answered in the video (I couldn't find the answer): assuming you have two ground plans (SGGS), I see how return vias are needed to reduce noise for signal traces, but what about power traces? I suppose that return vias for power traces are either less important or not important. Is this correct? Edit: I asked ChatGPT, here's what it said (not sure if it's accurate)... "It is generally recommended to use return vias for power traces as well when switching between layers on a 4-layer PCB. The purpose of a return via is to provide a low impedance return path for the signal or power trace, which helps to reduce electromagnetic interference (EMI) and noise. When a signal or power trace is switched from one layer to another, it can create a discontinuity in the return path, which can result in high impedance and unwanted noise. By using a return via, the return path is maintained and the impedance is reduced, which can improve the signal integrity and reduce noise. In addition, having a solid ground plane on layer 2 and 3 can also help to provide a low impedance return path for the power traces, which can further reduce noise and improve performance. It is important to carefully consider the layout of the PCB and the placement of the return vias to ensure proper grounding and signal integrity."

[@schmetterling4477]

What you are losing by not using a power plane is the distributed capacitance. A power trace incurs tens or even hundreds of nH of series inductance and even a bypass capacitor rarely has less than a few nH of series inductance. Only a sandwich of power and ground planes can improve this problem. Return vias will do absolutely nothing about it. Some people think that this won't matter for analog circuits, but it does. There it's not the trace inductance that will get you but the trace resistance. I dare you to simulate the distortions of an op-amp circuit with and without 0.1-1Ohm series resistances in the opamp power supply lines. See if you can get the second and third order harmonics at 1kHz down to the -110dB level as the data sheet promises for your $4.50 precision analog opamp if you mess up the power system impedance. Hint: using a 30 cents part with power planes would have been better and it would have saved you $4.20. ;-)

[@87Spectr]

IT'S LEGENDARY! 😀

[@weeeeehhhhh]

What about a 6 layer PCB of SGS SGS, where layer 1-3 and layer 4--6 are tightly coupled, with vias between 2 and 5?

[@greid666]

Eric i think you were misundersranding roberts question about the voltage of the power plane. I think he was ttying to say when referencing a power plane does referencing a power plane that doesnt power thr chip where the signal is coming or going vs referencing a power plane that does. Example being a pair of 3.3v chips but there signal is referencing a 5v plane vs a 3.3v plane. Since tge 5v plane doesnt have a DC connection to chips that genetated the sigbal wont that cause issues?

[@evolutionarytheory]

Most tools that compute impedance require knowing the nearest distance to the ground on the same layer. How can you use those tools without copper pour?

[@Motorman2112]

What are you supposed to be connecting the stitching vias to if not to a copper ground pour on both sides? Should they just remain unconnected on the top layer?

[@mumbaiverve2307]

Thanks a lot Robert and Dr.Eric. I did not quite understand the concept of the return via, between the signal via @41:09 . Is this just a via connected to ground and placed between 2 signal vias ? Sort of like the cable connected to ground and running between 2 signal lines in a flat ribbon cable (to reduce cross talk) ?

[@RobertFeranec]

If I understand your question right, then this video may help a lot: kzbin.info/www/bejne/rKPXZJ-Casx4mJI

[@mumbaiverve2307]

@@RobertFeranec Thanks Robert, will watch it !!

[@jimjjewett]

This explains why you wouldn't want to use power planes as reference planes, and that lots of copper ground fill isn't as good as not having to change references during the return path. But what are the real alternatives? (1) With routed power traces, wouldn't the power traces themselves change voltage often enough to cause noise, and to do it on the signal layer, without a ground in between? (2) Are extra ground pours actually harmful, or just not helpful? If you have the space, and are deciding between ground pour and no-copper empty space, is there a reason to prefer the empty space?

[@andymouse]

you ask a great question (2) don't they answer that ? aint watched yet !

[@jimjjewett]

@@andymouse If they do, I missed it. Based on another video (I think it was Zach of Altium interviewing Eric Bogatin, or maybe the comments there) it was suggested that ground pour would be better if you did everything perfectly, but leaving the space blank is almost as good and much less error-prone. (For example, the ground pour can make things worse if you do leave a gap in your stiching vias.) But I still feel like I'm reporting a rumor instead of *understanding* why you wouldn't want more pours.

[@andymouse]

@@jimjjewett Thanks ! to me pours are a good thing in most instances.

[@chromatec-video]

@@andymouse Yep have to agree with you. From a fabrication perspective, pours avoid over-etching. From an assembly perspective, maximising pours help to avoid warping.

[@mayankamipara6766]

Will you please make the pcb design video for power electronics application, for high switching current and voltage.

[@優さん-n7m]

I know about things like johson noise, but really is di/dt noise? I do not understand.

[@teechui2401]

@1:55 I can smell this image 😆

[@josesaumell2908]

Following up on my previous comment, for the claim of 100mil trace for 10Amps, over 10cm length PCB we would need to design for 50 degree temperature rise and we would loose 1.8 watts on that trace. Am I missing something? Can someone corroborate the numbers?

[@richardreel]

Very much appreciate these videos. PLEASE, Robert, try to interrupt less. Never is ideal, but maybe 1/3 to 1/5 as often.

[@schmetterling4477]

Plane layers are dirt cheap these days, so use them. I usually do six layer boards for analog right now. Why? Because it means I don't have to think even for a split second about power, ground and routing... there is just space through the roof. What's the cost of that? A couple bucks for a small board. Unless you are in a production environment absolutely nobody cares about that money.