Excellently explained! Made clarity on body biasing technique and current VLSI industry needs. Thanks for the Video ST Electronics!
@souvicksaha17538 жыл бұрын
Excellent illustration and explaining.
@sunilht19908 жыл бұрын
With less effort I come to understand a Very good concept
@muniswamy1004 жыл бұрын
Thanks indeed for a wonderful illustration. Saved tons of reading effort.
@7th_dwarf54210 жыл бұрын
Well done STM. It would be interesting to see how this implementation of the process compares to the tri-gate of the same technology node.
@Torchl1462 жыл бұрын
Thx STM for this great video really intresting and very well explained for someone completly new to this technology
@olympuspamir572911 жыл бұрын
Thanks for this video. It helped me a lot to understand the FD-SOI. Thanks!
@centuriomacro9787 Жыл бұрын
Thx, the visualization is very insightful.
@SethavutDuangchan9 жыл бұрын
thank you for easy explanation that it's very good video.
@alexvour4509 жыл бұрын
one think i didn't understand in the video: how is the lithography reduced when using fd-soi? by what means? it appears as if you switch to fd-soi and automatically the lithography is reduced.
@sunilht19908 жыл бұрын
But how the power dessipation can be reduced with different body and gate voltage? Can anybody Explain please :)
@prjthkmr7 жыл бұрын
I think they are talking about increasing the Vth for devices by body biasing so that the subthreshold leakage can be reduced.
@anilkumarpattapu79844 жыл бұрын
@@prjthkmr I think subtheshold current will not happen due to insulator below the channel that makes fully depleted... correct me I iam wrong
@rockon17819 жыл бұрын
very appreciating video..loved it..
@kartikR115 жыл бұрын
Going to help in my university exam. Thanks
@ravi9diamond12 жыл бұрын
Awesome Video & Ultimate technology. Explanation is really simple. :) :)
@Sky945674 жыл бұрын
very good video...
@jizanthapus1763 жыл бұрын
Thanks a lot!
@JD-kf2ki3 жыл бұрын
Isn't this a Swiss-French semiconductor company?
@বাঙালিরস্বপ্নেরক্যানভাস2 жыл бұрын
I have one question, how to mitigate the latch-up problem in SOI structure devices?
@eduardorocha84606 жыл бұрын
bão dmais , obg memo
@textex201012 жыл бұрын
Greate vídeo
@gyzq2 жыл бұрын
10 years later, you still can not deliver 14nm FD-SOI👿
@sebastianelytron84507 жыл бұрын
Superb video, shits all over Intel's education vids