An introduction to FD-SOI

For more info bit.ly/ST-home-tag
This video is an introduction to FD-SOI (Fully Depleted Silicon On Insulator), and especially UTBB (Ultra-Thin Body and Buried oxide) produced by STMicroelectronics. FD-SOI is a breakthrough semiconductor process technology that delivers the benefits of reduced silicon geometries while enabling a simplification of the manufacturing process. Semiconductor devices based on FD-SOI run faster and cooler than those in bulk silicon.
Unlike some other technologies, FD-SOI does not change the fundamental geometry of the transistor. In FD-SOI, the innovation lies in adding a thin layer of insulator, called the buried oxide, positioned just below the channel-the UTBB. This buried oxide layer eliminates the need to add dopants to the channel, thus making it "fully depleted."
The video explains some of the challenges of transistor design and how FD-SOI meets these challenges in a simple and cost-effective way today.

[@vadakkodan]

Excellently explained! Made clarity on body biasing technique and current VLSI industry needs. Thanks for the Video ST Electronics!

[@souvicksaha1753]

Excellent illustration and explaining.

[@sunilht1990]

With less effort I come to understand a Very good concept

[@7th_dwarf542]

Well done STM. It would be interesting to see how this implementation of the process compares to the tri-gate of the same technology node.

[@muniswamy100]

Thanks indeed for a wonderful illustration. Saved tons of reading effort.

[@Torchl146]

Thx STM for this great video really intresting and very well explained for someone completly new to this technology

[@centuriomacro9787]

Thx, the visualization is very insightful.

[@olympuspamir5729]

Thanks for this video. It helped me a lot to understand the FD-SOI. Thanks!

[@SethavutDuangchan]

thank you for easy explanation that it's very good video.

[@kartikR11]

Going to help in my university exam. Thanks

[@rockon1781]

very appreciating video..loved it..

[@alexvour450]

one think i didn't understand in the video: how is the lithography reduced when using fd-soi? by what means? it appears as if you switch to fd-soi and automatically the lithography is reduced.

[@jizanthapus176]

Thanks a lot!

[@Sky94567]

very good video...

[@sunilht1990]

But how the power dessipation can be reduced with different body and gate voltage? Can anybody Explain please :)

[@prjthkmr]

I think they are talking about increasing the Vth for devices by body biasing so that the subthreshold leakage can be reduced.

[@anilkumarpattapu7984]

@@prjthkmr I think subtheshold current will not happen due to insulator below the channel that makes fully depleted... correct me I iam wrong

[@ravi9diamond]

Awesome Video & Ultimate technology. Explanation is really simple. :) :)

[@eduardorocha8460]

bão dmais , obg memo

[@textex2010]

Greate vídeo

[@JD-kf2ki]

Isn't this a Swiss-French semiconductor company?

[@user-zs1yd7xg9m]

I have one question, how to mitigate the latch-up problem in SOI structure devices?

[@frankgoh2865]

видео полезнен

[@sebastianelytron8450]

Superb video, shits all over Intel's education vids

[@gyzq]

10 years later, you still can not deliver 14nm FD-SOI👿

[@jedipdx]

Google Pixel brought me here. 👽