Gate-All-Around - The Future of Transistors

[@xlerb1637]

Not an electromagnetic field, an electric field. An electromagnetic field always means photons (light, microwave, radio, etc.) no exceptions. That's why it has the "electro" part and the "magnetic" part; photons are an alternating electric field and magnetic field. Field Effect Transistors just use an electric field, that is, a charge. Nothing magnetic.

[@HighYield]

Of course, you are right. Thanks for the correction!

[@PaulSpades]

The EM field includes magnetic and electric oscillations, if you must call them photons, fine. Electric and magnetic are components of an EM field/wave, but they are not proportional. You can have electric effects without much magnetic effects and the other way around. The proportion of these components depends on geometry, material and other properties of the effector and medium. FETs don't generate MUCH of a magnetic efect, NOT none. Your comment is like the inverse of astronomers measuring magnetic fields in space and concluding that there's no electric current flowing because the magnetic effect is weak. Kilowatt lasers also generate next to no magnetic effects.

[@xlerb1637]

@@PaulSpades ? A kilowatt laser would have a kilowatt of magnetic flux (as well as a kilowatt of electric flux) but it would be nearly undetectable outside the photons. A FET generates no magnetic field, except a negligible field when the charge is impressed or removed.

[@EntekCoffee]

​​​@@PaulSpades That's a good analogy, but regardless, there should be a clear separation between electric, magnetic, and electromagnetic fields depending on context. In the context of FETs, I don't think electromagnetic and electric fields are interchangeable, but these mistakes happen.

[@PaulSpades]

@@xlerb1637 All true. A 1kw laser generates 0.00133 tesla when hitting a surface (assuming perfect absorption): a small bit stronger than a fridge magnet. The FET generates EM when switching(which should cause tiny EM ripples). But also caries electric current when conducting, and you can't have electric current without magnetic waves, as small as they are.

[@Asianometry]

4:43 ❤ High Yield is by far the most handsome and smartest of us two. Don’t be deceived!!!

[@amessman]

"The last time it happened was over a decade ago." _shows FinFET_ I'm getting old.

[@satibel]

2014, that was like 2 years ago, no?

[@JorenVaes]

I'm working on a GAA tapeout right now. From an analog designer's perspective, the transistors perform great, but my god the ever increasing layout rules a nightmare. In addition, the lack of multiple oxide thicknesses makes anything that faces the IO a significantly higher challenge. In all honesty, I think back-side power will have a significantly higher impact on performance than the move to GAA.

[@HighYield]

You think software/EDA tools will at some point take over when it comes to chip design? Like no more humans needed?

[@JorenVaes]

​@@HighYield I don't know to be honest. You already see this in digital design - more and more of the design is shifted to 'programming'-like, with HDL and such. That said, the standard cells are still often done by hand. In analog, it's a mixed bag. You do see companies trying to push this - though in most cases it is from a 'design-portability' perspective - being able to easily migrate a design from 16 to 10 to 7 to 5 nm, or make small variations (more output driver power, higher current capacity of an LDO, etc). But, at least as far as I understand it, you still do use a lot of manually designed. Even if they are just generation scripts, the best trade-offs in those rules are made by thinking and designing 'the old fashioned' way. When it comes to high speed analog, it is similar, though I think as you go higher and higher in frequency, I think you see less and less automation, as there is more 'fingerspitzengefühl' involved in the desing process. The few attempts I've seen to fully automate the design process have been mixed. I imagine AI will eventually get there, but I don't see it happening in the next 10 years. That said, if you asked me 10 years ago if I would be able to have a pretty convincing conversation with a chatbot by openAI about the intrecacies of millimeter-wave design, I would have laughed you out the room but here we are. ---- What I can say is that with these new nodes, the layouts for analog are starting to look more and more like digital design. Where it used to be you really could tell the individual transistors and so on, you now see more and more that people just create a sea of transistors, all next to each other in a huge grid, and then are connected. In the most recent nodes (like 10 and below) you are pretty much forced to do this, as the multiple-patterning required for forming the gates requires huge repetitive patterns. Usually, these designs also use negative layers, called cut masks - you have huge poly or metal lines that are like 5 um long (which is massive compared to anything else in the FEOL in a 10 nm technology), and then you have a pattern of 'cuts' every 200 or 300 nm that defines your standard cell hight. You also don't get to just chose a transistor width or length - you might have one or two lengths, and two or three widths to chose from. Want a wider transistor? Put more in parallel. Want a longer one? Put them in series and pretend it is a longer gate.

[@DerIchBinDa]

@@JorenVaes Thank you that was really helpful for an interested outsider to better understand how the process of design works.

[@kevikiru]

It's clear that High Yield's first language is not English yet he is so eloquent in speech. Even more interesting is the fact that he is speaking about complicated language to probably a technically competent audience but not very sophisticated but still very understandable. And he keeps attention without the repellent clickbait and over-hype. This is just lovely!

[@andrebrait]

The fun part about being a 2nd language speaker is that you can feel absolutely confident in the domain you're used to and speak about it in detail... But then you can't ask someone to pass you the thingamajig at the table because you never used the what-you-may-call-it and it's right next to the thingy you absolutely know but never had encountered the translation before. I can talk about technical stuff in English better than I can in my native language, even 😅

[@hornsteinhof7592]

Indeed. Is he German perhaps?

[@TechOtakuYT]

Not to be rude but this comment section gives me brainrot 💀

[@m1ar1vin]

Yes

[@kevikiru]

@@TechOtakuYT Maybe your brain was already rotting and you just realized now and having a knee-jerk reaction

[@IamTheHolypumpkin]

Wait, how do I notice this only now. You where my University Professor I took my "Wahlpflichtmodule" using FPGAs. Still the most fun modules I ever signed up for.

[@Executor009]

So is he German? I kinda thought that by the way he pronounced wafer.

[@themuch21]

​@@Executor009 He sounds pretty german to me.

[@blueboy3990]

Dang ASM looks so cool ! I am definitely buying one of their machines, but I'll have to wait till black friday for the discounts !

[@HighYield]

I should have a 10% code ;)

[@1samm1]

​@@HighYield if you'd get a percentage of their sales - instantly made for life 😁

[@karlstathakis7786]

This is rapidly becoming one of the best channels on KZbin.

[@donsknots6510]

We laugh but itd just get scalped ​@HighYield

[@AnalogDude_]

lol

[@DigitalJedi]

Hello once again from Intel Foundries! I've been loving to see all the coverage these new nodes are getting. Intel has moved me on from 18A fully now that Panther Lake has powered on. I don't have all the info and can't give all of what I do have, but I'm happy to field questions again.

[@eddiedoesstuff872]

Always cool to see an expert in the comment section! Anyways, from what I’ve seen, every new transistor innovation just increases the amount of contact space between the channel and gate, but since we’re already surrounding almost every side of the channel, is this it for transistor design or are there other possible avenues to increase efficiency?

[@vicktran669]

Is Panther Lake the successor to Arrow Lake or Lunar Lake?

[@EntekCoffee]

I don't know whether or not this has been asked (or published) before, but I'm curious on how you guys build the metals of the M-I-S gates scalably. I work with Si fabrication too and I just couldn't imagine how you guys wrap the metal around a suspended channel like that, at a huge scale with good yields! Is ALD that good now?

[@DigitalJedi]

@@eddiedoesstuff872 This isn't quite the end, but we are beginning to approach what I would consider an "endgame" transistor design under current manufacturing processes. BSPDN and other technologies to optimize other parts of the chip outside of the transistor scale are going to become very important, which is part of why intel is investing heavily in them now. Advanced packaging and power tech are likely going to be as big a part of a truly next-gen node as much as transistor density is. Being first to the market with combined BSPDN and GAAFET also means they have a headstart on an improved version, which is where the rubber really meets the road.

[@DigitalJedi]

@@vicktran669 Ideally it succeeds both as an 18A product with new cores and Xe3. I sadly can't say more about it than is already out there.

[@bastiangugu4083]

Great shoutout to Asianometry. His videos are always very interesting, not only on semiconductors. 🙂 But I'm also very glad to have found your channel. It was through a video by Tom from MLID. So the journey continues.

[@Asianometry]

You’re too kind

[@christophermullins7163]

When you said "thats the 'field effect'" many things vame into perspective for me. You do such a great job explaining these topics. ❤❤❤❤❤

[@HighYield]

Awesome, thank you! Really helps getting that feedback :)

[@hytalefanboi7471]

It's a good day when High Yield drops a new vid

[@ADB-zf5zr]

Always.

[@karlstathakis7786]

Hell yes it is

[@jemborg]

Yerp

[@sokiuwu]

Can't Wait for 4D transistors

[@IDTT137]

They'd probably find a way atp

[@sgt_mate]

Took me a few minutes to bring back my knowledge on fet but I think I got it now. Thanks for bringing back and enriching my knowledge.

[@EntekCoffee]

Nice video! One detail you might have missed is that in GAA, assuming that it's a perfect structure, you can have multiple different FET channels coupled together by one gate. This could be handy in many situations. If individual channel growth is controllable enough, you can also have multiple independent FETs in the same area of what used to be one FinFET. This would increase transistor density exponentially. Plus, you can also make FETs that interacts with each other vertically through simple or even quantum (!) interaction! It's Sci-Fi for now but many research labs are very successful in these already (especially in sub LN2 temperatures). However, the issue is with cost (which implies simplicity). The very reason why Silicon has been the material we all know is that we can get away with as little epitaxial growth as possible. It is the jack of all trades that is extremely cheap and easy to work with. Consequently, the traditional "silicon planar process" never included any epitaxial growth, except for the metal parts. Only etching, doping, oxidation, and lithography was needed.

[@MFMegaZeroX7]

While certainly unproven, Rapidus is also supposed to start producing 2nm in 2027 presumably using GAAFETs. It would be interesting to have 4 cutting edge foundries if they can do it.

[@aaronrocs]

Crazy how much work went into you being able to watch cat video's while you're supposed to be working, or reading, or going outside, or cleaning.

[@shuginubi]

Just thinking about the indomitable human spirit willing to take on such an immense task as wrapping those tiny channels. Just mind blowing.

[@shmookins]

Ah, you abruptly stopped at the forksheet/fork design. I was so engrossed in the whole video and was very curious about this new fork method. Excellent video, friend. I'm off to look for this fork idea.

[@HighYield]

Definitely a future topic!

[@karlstathakis7786]

This is rapidly becoming one of the best channels on KZbin

[@dirg3music]

Yeah these hardware deep dives are incredible

[@rogerhuston8287]

GAA marks a significant step, but I'm a bit more excited about adding back side power delivery to the process which should also help with manufacturing.

[@Vinzmannn]

I think this was a nice explanation. Also really nice of you, shouting out a much smaller youtuber like asianometry.

[@paulnewhouse5126]

Good to see you on Moore's Law is dead man! Hope to see more content from you soon.

[@gustamanpratama3239]

Such a ❤❤❤❤ly thorough summary! Please a video on the differences between VTFET and CFET

[@Techaktien]

Excellent Video. Thank you.

[@saewings4963]

Again, thank you so much for Korean subtitles

[@cube2fox]

I believe it was around the introduction of FinFET when the trend of exponentially decreasing cost per transistor broke. The introduction of GAA and backside power delivery could also have a substantial impact on manufacturing cost.

[@oIdspice]

feed me transistor knowledge and I shall consume

[@PushyPawn]

Much respect for all the clever silicon boffins who are keeping Moore's Law alive, albeit at a more reasonable pace. Now to securely plug all the holes and stop current and future IP from leaking to the CPP and terror-ruzzia.

[@erkinalp]

russia is not that far behind in silicon R&D, they just don't invest into high volume manufacturing to affect the stats significantly china has its own leading edge R&D and full scale fabs

[@PushyPawn]

@@erkinalp You're funny. Do you do stand up? Where can I see you?

[@timl2k11]

Like that it’s not just a disembodied voice in this video.

[@HighYield]

Maybe I'm just a clever AI?

[@Adrenaline_chaser]

​@@HighYieldit might well be. Nowadays I can't trust anything anymore, AI is getting out of hand 😬😬

[@MrJonaslaCour]

Kudos for giving credit to other KZbinrs where it is due

[@a.m.g.r7804]

Thank you for sharing this in such a summarized and collective manner. I have always been fascinated with technology on a fundamental level of how everything actually works and is manufactured, including trying to understand what’s coming around the corner. I’m in real estate but always wanted to get into IT as a Sys and network engineer and to advise a corporation in which platform to invest in for its back end servers, I remember seeing AMD at 3$ and I told my boss tell the owner (who also has a investment division) to invest in AMD way back in 2016 since I knew AMD will be getting back into the game now it’s at 162.

[@AdvantestInc]

The discussion on the challenges and benefits of Gate-All-Around transistors highlights the industry's ongoing innovation. The transition from FinFETs to GAA transistors is crucial for advancing power efficiency and performance. It will be interesting to see how leading companies drive this technology forward.

[@varno]

I would argue that the dhift from ttl to mos, the move from nmos to cmos, and the introduction of deep trench isolation were all significant structural changes to ic production, but conceed that the move to progressively more 3d transistor channels has only happened twice now.

[@Nuiiiiiiiiii]

I really like this channel, you do an excellent work searching and explaining this complex subjects for people like me that are not engineers. I think majors improvements like use to be in the 2000's/2010's aren't posible anymore but, they really not surrender xD.

[@HighYield]

My goal is to focus more on KZbin in the future, because it’s difficult to produce quality videos alongside a normal job.

[@douro20]

ASM doesn't just make ALD equipment. They are also a leading producer of epitaxy tools including specialised tools for epitaxial growth of silicon carbide, a technology they acquired with the purchase of Italian firm LPE in 2022. They also make vertical furnaces and equipment for plasma enhanced CVD.

[@HighYield]

Seems like Samsungs "mystery" first GAA chip will be the Exynos W1000 for the next Samsung Watch: semiconductor.samsung.com/processor/wearable-processor/exynos-w1000/

[@elaijah4622]

Getting sponsored by ASM is uniquely crazy

[@kellymoses8566]

Can't wait for a 18A gate all around chip with backside power delivery

[@nikbl4k]

Hey, still very informative. Thank you, keep making videos... Its illuminating to learn these thinhs.

[@ADB-zf5zr]

I would like to see Mr High Yield do some more collaborative work / discussions with other people. I have watched two with MLID (Moore's Law Is Dead) and IMHO they are two of the best three videos of MLID's discussion videos I have watched. Your ability to describe and to teach is IMHO excellent. Now onto the video talking about the primary change that chip production is (forecast) to face for 10-years (which is huge compared to when chips (semiconductor transistors) were first created back in the 70's), this IMHO is going to be a massive change and it is not just down to who is fabricating the chips, far from it, it is an absolute foundational change in chip design and if will be a bumpy ride for a while as chip designers fall into unknown traps, and others dodge them by luck. The engineers will learn and in a way, those coming in second with a simple product will likely win heavily as they gain from others mistakes and make none themselves. As for the big companies, what will happen over the next few years may force a company into destruction, or create the perfect conditions for a revolutionary product to soar. As is always the case in this industry, the future looks to be very interesting, and as GAA spreads, morphs, and vartious versions are designed and rtested by various companies, they themselves will be ironing out the bumbs as they release products, so as always, consider product one to be a comercial scale test and proof of concept whilst putting a new product to market and having 100 refinements happening simultaneously, but it will take a fundamental (revolutionary) change in design and/or manufacture to make the proof of concepts into a tuned and refined product likely sometime in 2025 this iteration of GAA will become fruitful at the msaa market level, what comes next will likely be the refined version and offer real world benefits that bring this new manufacturing technology to the masses.

[@How23497]

Collabs would be great, but MLID is a clown, has he even got anything correct on release?

[@crysed7897]

MLID.. Oh no please

[@LeonardTavast]

@@How23497 Yep. TechTechPotato and Asianometry are much better youtubers than MLID.

[@noobgamer4709]

@@How23497 and have you even got any info not from leaker that true on release. that guy got somethings wrong but not sure a clown cause the only one i see here is you. guy got 10% right and 90% wrong are still better than 0% right and wrong. Leaks meant to change even till the last millisecond before the company present/release/launched. youre probably from wccftech and hey, your next rtx5090 can be 1599$ till jensen decided to change to 2000$ before telling the price

[@pneuma23093]

Asianometry face reveal????

[@gendalfgray7889]

So if you make more edges on gate it becomes better? They should try some complex shape

[@stefanweilhartner4415]

it will be interesting if this also brings advantages for power transistors. less resistance, higher switching speed?

[@AnimaChronix3]

Love ASM/ASML !

[@Alorand]

First time I don't get how the sponsor (ASM) expects me to act due to their sponsorship. Are KZbin viewers going to buy a Fab?

[@HighYield]

While you could buy a ASM Atomic Layer Deposition tool for your living room, I think it’s more about brand recognition. Now you know them and what they do. Plus, you know they do really cool stuff.

[@iamtimsson]

also Understanding error handling may be a significant difference between the easy perception of an action between an automated source and non-automated source.

[@kniazjarema8587]

4:52 There's no link in video description.

[@HighYield]

I’m not referring to a link at 4:52. can you explain what you mean?

[@Behnam_Moghaddam]

Thank you for yet another very informative video! btw: Zollstöcke geben vorzügliche Lav-boom-arms ab, falls die Lust zum mikrofesthalten mal vergehen sollte.

[@benbreeck3363]

Hmm.. I will stipulate that Gate All Around FET is the cutting edge and future of semiconductor transistor design, but I wonder what benefits the design method would be/would have been realized on larger, back endof the line nodes. Fin FET designs seemed to mean denser interconnects beteen transistors for a given node and density. Am i reading tnis correctly?

[@AlexK-jp9nc]

He mentioned it in passing but it seemed like there's now the ability to make 3-D chips that use the vertical direction in many layers. Basically a cube instead of a wafer

[@greebottle]

Great video! Does forksheet gives a sufficient improvement for a standalone node, or will it be more of a half-node at best or perhaps the industry will transition from GAAFET straight to CFET?

[@dgillies5420]

40 years ago in VLSI for poets class I was told that the electric field draws electrons and holes up from the semiconductor substrate allowing current to flow in the channel. I don't understand where those mobility carriers come from in GAA ...

[@EntekCoffee]

With masking you can selectively dope the nano-scale channel with acceptor, donor, or both atoms. If you apply enough electric field, you can deplete, accumulate, or invert the channel, increasing/decreasing its conductivity. The same thing happening in a regular FET.

[@PunmasterSTP]

Seems like there's more than one side to this story 😎

[@MarkBarrett]

They are going to hit a limit on the nano-meter scale node shrinks, that an atom is around 0.3nm.

[@playbutton108]

i have two questions 1. Are we sure that transistor are working like transistor at nm level . I have a theory that they are working like vacuum tubes now current heats up the gate and current flow. dielectric changes into conductive. 2. why don't we make just create small vaccum tube or transistor like concentric circles .vaccum tubes will have 4 layers and transistors will have 3 layers.

[@naikrovek]

this is a fantastic video, but why are you *holding* a clip-on lapel microphone?

[@diraziz396]

Great coverage Thanks

[@tommihommi1]

the changes to power delivery that are coming alongside the switch to GAA might have a at least as big an impact

[@maynardburger]

Pretty sure Arrow Lake S and mobile is still this year, so Intel should probably be the first manufacturer to offer a consumer/mainstream product using GAA. That said, 20A which is expected to be used for just the CPU die, is likely gonna be in a very '1st gen' phase, so might not really show off what it can do. 18A is basically what they'd have previously called 20A+, and that's likely where we'll see Intel and GAA/BSPD starting to really demonstrate the advantages and get back into a proper competitive position.

[@Ghostsonplanets]

Arrow Lake 20A is only Desktop 6+8. Everything else is TSMC N3B. And ARL Mobile is CES 25

[@azamatbezhan1653]

How do you think, when forksheet fet with Full bottom dielectric isolation will come. Impact of self heating effect in bottom dielectric isolation is not overcome

[@PreacherGannon]

If the gate wraps around 3 channels, and is energized to create a field to allow the channels to flow... how do you make 1 channel flow while the adjacent stacked channel cannot flow? Do you have to time it so all 3 channels can only open at the same time and like ... idk air traffic control bits so all 3 channels only open for flow at the same time but only the 1 channel you care about at this 'moment' is energized to transmit by a preceding gate? (where a moment is some insanely small fraction of a second)

[@TCruh]

You missed the chance to say "And this is a very Intelesting one..." on 9:21

[@kurtu5]

FinFET? Well, guess I was paying that much attention to solid state physics for the last 15 years? And now this, and then that? Nice.

[@pham3383]

i'm a power electronics engineer,love the thing computer engineers doing

[@TechOtakuYT]

Man, it wasnt long ago when 14nm was revolutionary for using FinFet technology, now we will be switching to a new design again. Moore's law might be dead but not technological advancement

[@alphaspace1100]

Always a pleasure

[@boazbrisker81]

Great video 🙏🏻

[@Jaker788]

What about contact over active gate? Is that the same concept as this or is it something else? From what I understand, Intel tried it initially on 10nm but dropped it due to yields among other tech that wasn't working.

[@PeterRince]

Interesting stuff. Thanks!

[@Redtoad1234]

It's interesting to see Dutch equipment suppliers advertising to the public so much. I assume they're just trying to juice their stock or looking for more subsidies from the EU/Dutch government.

[@kuuhgle]

Does ASML still make the machines for this new tech?

[@WilliamTaylor-h4r]

Should call it channels so you don't have to guess the grey piece does work, like the old ship yards.

[@Bleats_Sinodai]

In the end, it all goes back to the vacuum tube 😊

[@gustavoromo6879]

How different will the code be?

[@quegyboe]

My guess for the leading SoC being made by Samsung is their next Exynos 2500.

[@MarkBarrett]

It is the surface area that they want.

[@satibel]

my guess would be an exynos chip, as samsung would be able to have the most experience with their own process

[@HighYield]

Yes, it seems to be the Exynos W1000 for the next Galaxy Watch.

[@David-ty6my]

A German talking to the camera in english so that I, another German can understand it ❤😂

[@HighYield]

Und es klappt auch noch 😄

[@iamtimsson]

hello. calls i him. goes good you? have you yet the video liked? hears and sees me good this video! yes yes. meatstick haha

[@Ishpreetb264]

Samsung is rumoured to use SF3 based chips in the galaxy watch 7 series.

[@Artofficial1986]

I love the NHI tech

[@enrac]

Is ASM the same as ASML

[@my0wn0p1n10n]

No different companies, but they have historically the same roots -> Philips

[@enrac]

@@my0wn0p1n10n Ah okay, thank you. I was looking for ASM's stock symbol, can't seem to find it, the only other ASM is some mining company.

[@HighYield]

They are not, but way back in the 80s ASM and Philips founded ASML. Tho today they are different companies.

[@eruiluvatar236]

As they are growing them layer by layer I wonder if there is anything stopping them from growing more than one layer of transistors achieving true 3D. That would allow them to push density per mm^2 when making smaller transistors is no longer possible and thermally it would be better than current stacking solutions, specially if they tune the transistors for efficiency instead of speed and go for way more transistors as a trade off.

[@jannegrey]

They already do that - at least sort of. Even with etch it is doable. After all we moved to this (couple layers of transistors on top of each other) a long time ago. This is what decoupled "nanometers" from gate size.

[@davidgunther8428]

They do this with NAND flash memory, but I think the transistor quality is not good enough for high performance logic.

[@jamegumb7298]

The real shift I think will come with the integrated tiny capacitors they recently came up with. Another: optical interconnects, like the experimental Intel 4Tbit one. PCIe over 100m.

[@sunefred]

Now that the transistors are deposited and no longer masked or etched from the wafer, why do we even need silicon wafers? Could they not be made of anything really?

[@pettanshrimpnazunasapostle1992]

Silicon is used for its semiconductor property and abundance compared to other semiconductors. Not just because it can be etched into easily

[@sunefred]

@@pettanshrimpnazunasapostle1992 But thats my point, the semiconductor properties were useful when being doped by gallium or germanium to create the transistor. Now, with the transistor no longer being created from the wafer material, whats the point?

[@iamtimsson]

I mean if we can place atom by atom, but what does it mean to have an arm?

[@tomstech4390]

Waiting for foam transistors now.

[@jeffbuckles]

Quantum foam, maybe. Remember, buzzwords make the investment world go 'round.

[@benzed1618]

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOoooooooooooooooooooooooooooooooooooooooooooooooooooooo

[@novantha1]

While very technically interesting, I wonder if it's a true advancement, or an extension of existing technology. What I mean, is that for instance, a 14nm product is fine, and, all other things being equal, you would expect a 7nm product to be twice as good. Surely. But if the cost per transistor is analogous then when moving to the 7nm product you either get something half the size at the same price, or you get something better at a higher price. The manufacturing around GAA transistors sounds really expensive. I wonder if there will be gains that trickle down to us humble consumers.

[@arianamirgholami9555]

9:07 pretty sure it's the next exynos chip but because of yield problems most likely it won't find its way into next flagships

[@HighYield]

Good guess, makes a lot of sense.

[@M4xFr4gg]

​@@HighYieldI would guess, it's the next Google SOC. Clearly shared heritage and as such probably easiest to adapt to new Samsung processes, but given Google's market position not as much volume as the Samsung Galaxy S devices.

[@RecoveringNihilist]

Every time people start saying Moore's law is dead.

[@tobywoolsey7844]

When people say that it’s kinda out of context. “Mores law is dead” comes from the fact that we are at a point that chips made from larger nodes can achieve close or the same performance of the smaller nodes due to advanced architecture and packaging. Also I think it came from the fact that we are close to 1nm which is probably the limit for any chip.

[@ChibiKeruchan]

These kind of changes is the reason why it feels like the devices we buy like 5 to 10yrs ago is more durable than what we have now. expect some of your devices who uses these new design to break faster than what we have now. it's the changes we need to accept and support until the design finally went to it's final development and improvement in the next 10yrs.

[@NootNoot.]

Wah, different upload time. Looking forward to watch this one, a hotly anticipated topic with 20A nearing!

[@HighYield]

Last time was in Taiwan, this time I'm in Germany again.

[@NootNoot.]

@@HighYield Haha, well that explains the background change and lavalier mic

[@wile123456]

I'm guessing the mobile chip at Samsung foundry is an exynos chip by Samsungs mobile division. I doubt apple would use Samsung, since they have premium relationship with TSMC newest nodes. Qualcomm also uses TSMC. Samsung has fumbled their nodes a lot the past 5 years, being a generation behind TSMC in effeciency, the snapdragon 8 gen 1 etc was a failure of a chip, having worse effeciency curve than the previous 888 chip, and only getting more peak performance because they raised the wattage

[@Illumina_Blade]

What's all this about Trains?

[@csvscs]

Google is my guess for the samsung chip

[@supernovahm1178]

When I was like 8 I thought that "fin" FET's were named as such, as a kind of mispronunciation of "thin". Stupid sure, but I was young - and as a result I have always been aggravated by the name.

[@johnmanderson2060]

Don’t hold your mic, attach it to your t-shirt collar and run the cable inside the t-shirt. It will free your hands for gestures when talking.

[@HighYield]

It’s not my usual setup, I recorded in my GFs apartment. And I didn’t want to spend the extra time setting it up 🫣

[@kineteks77]

Or, do whatever you want. Good video, sounds great.

[@cocolasticot9027]

I can wait to buy my new pc. Just another few years... Again 😅

[@suhaimiseliman8593]

READ....ONLY 1 CHARGE LEVEL. WHAT'S THE ADVANTAGE OF HAVING > 1 OF THRESHOLD VOLTAGE IF WE CAN JUST INCREASE THE THE THICKNESS OF DIELECTRIC SO THAT GATE CAN HOLD HIGHER CHARGE LEVEL😊

[@aewcac]

What’s wrong with this idea? In cases where the output depends on the field of the gate, if the output is used between nodes that depend on the gate output, and there is no gate, the output between the output nodes would be OFF.. I guess that’s why it’s called “Gate~All~Around”. To make sure outputs between nodes without gates exist, reliable power sources would have to power the entire system, or at least power added hardware.

[@aewcac]

kzbin.info/www/bejne/a4Ozd5mGqcyqbcksi=7_lH1yIzRSgt2JD9

[@kayakMike1000]

No one tealy knows what John looks like

[@HighYield]

He's obviously a deer