The Semiconductor Design Software Duopoly: Cadence & Synopsys

[@earthwormscrawl]

I work for one of the big two, and while specific customers are a closely guarded secret, I can tell you that the number of companies that are designing their own chips would astound you. Companies that you would never think of as ever being in the chip business, because they're view as Internet companies, are designing their own chips. Decades ago it took massive amounts of staff and capital to design and build circuit boards, now anyone with a PC and open source software can send a file off to a PC board manufacturer and run their own small company. While we're still a ways away from that at the chip level, any medium size company can now design custom chips, starting with purchasing most of the internal circuitry instead of designing. The demand for EDA is about to explode as chip design becomes as common and board design used to be.

[@CarsMeetsBikes]

I agree with your last line, however unfortunately it's already priced in source: worked several years at one of the big two as well and stonks popped last couple years

[@eduardoramos8317]

❤​@@CarsMeetsBikes

[@CalgarGTX]

@@Rubicola174 I'm not an industry insider but, generally speaking, the bleeding edge nodes are used where extreme compute power is needed ie new best of the line CPUs/GPUs. TSMC wants firm orders from intel/amd/nvidia/apple for thousands of wafers of the same thing to keep their bleeding edge fabs running smoothly and profitably. But other than basically those 4, there are a million use cases out there that do not need anything close to bleeding edge. And in fact where bleeding edge nodes are a negative rather than a positive. If as a random exemple you wanted to make a chip that does FM radio + heartbeat monitor + 3G connectivity or whatever, it could be done on a 10/20+ years old node. But you would still need the tools to make the plans before shipping them to a fab.

[@lbgstzockt8493]

​@@CarsMeetsBikes Everything is already priced in. By the time you have thought of something some quant who makes 8 trillion dollars a year has already run 27 simulations and decidided to buy puts on every company involved.

[@Ordoscc]

I thought anyone can do chip design with FPGAs to play around with.

[@OperationXX1]

Good video. At the end of the video you asked “what changed” that ended the stagnation of these two companies, let me answer that question: what changed was the end of Moore’s law and the rapid rise of custom hardware. About a decade ago, there were only a few large chip design companies that could be a source of significant revenue for EDA companies , the likes of Intel, Qualcomm, Broadcom and Nvidia. That changed when Moore’s law slowed down and software companies, especially hyper scalers, started designing their own chips to gain performance through hardware customization and optimization. With rise of custom chips, the customer pool for EDA companies started increasing rapidly, companies like Google, Amazon and Microsoft started designing their own chips and would buy a ton of EDA licenses and design IPs from the duopoly. Also, more recently, a lot of chip startups, especially in the field AI accelerators, have been popping up left and right to design custom ASICs specialized for a specific use case to pursue significant performance increases. So, the rise of custom chip designs is the main driver behind the recent rapid growth of Cadence and Synopsys.

[@TheParadoxy]

Also Apple designs their own chips now! But I also wonder if integrating machine learning into the products is part of what's driving the growth. EDA might be delivering more value to customers if the machine learning substantially increases ppa. Additionally, the large training sets for machine learning might increase the barrier to entry for potential competitors

[@crashdavis4123]

fascinating, thanks 4 sharing

[@CarsMeetsBikes]

another point to add if you want to look on an even smaller scale post 2017 and around pandemic time, the chip shortage fueled EDA software sales as companies faced needs to design more efficient chips with tough material constraints. After that came AI hype in market which continues to drive the growth of the duopoly

[@CarsMeetsBikes]

@@TheParadoxy Apple designs their own chips now but that means they are coming to the source to buy EDA software. They are one of our big clients at the big two

[@Superalpaca1234]

To your initial point, any thoughts as to why the large players didn’t create their own EDA platforms? They would all have had the incentive and capital (unlike today’s hardware startups) to do so.

[@musicmakelightning]

How great to see EDA finally getting some widespread public exposure. I've been in EDA my entire adult life, working for both of these companies and others and the whole time, when people asked me what I did, I'd start to explain EDA, and then give up when they glazed over. Finally EDA is getting some public acknowledgement. Just in time for me to retire :)

[@johnmanderson2060]

Thank you for your service 👍🏻

[@geebsterswats]

lol. “So-Crates”. Someone was watching Bill and Ted’s Excellent Adventure recently!

[@glormymcglorm]

Ed the once called the rapper Saukrates "sow-crates" on Much Music and it had me in tears.

[@imtrueshot1]

Party on dude!

[@DerIchBinDa]

I am not sure if Asianometry know who Socrates was and that is why is mispronouncing his name. Tip: A Greek philosopher.

[@MrNilOrange]

I love Asianometry and soooo want to believe this is deliberate.

[@ivoryas1696]

​@@MrNilOrange I mean he says ARF and DRAM by the word, so I don't see why not!

[@ebrombaugh]

I was doing chip design from 1987 - 2004 and all this stuff is so familiar. Amazing how so much of what we did back then can now be done with web-based tools like those Matt Venn is providing with his Zero to ASIC course and Tiny Tapeout service.

[@henrybrandt1057]

One challenge faced by the two players is a very, very limited number of customers for their back-end tools, while the complexity of the ASIC and full-custom chip designs keeps increasing. So Cadence and Synopsys have increasing development costs in the back-end software just to keep up with each CMOS generation, yet there's no corresponding increase in the number of potential customers. There doesn't appear to be any obvious way to expand the market.

[@slickvik4508]

That's generally true but i would argue the opposite is why the gained so much in stock price. Hardware has become sexy again and there are many startups along with FAANG companies with hardware divisions. These companies rely heavily on EDA vendors to get off the ground.

[@stachowi]

@@slickvik4508 exactly, unlike ASML the cost of starting a Fabless hardware company is way more accessible than starting a fab.

[@JorenVaes]

Every man and their dog are doing ASICs these days. Volumes for a lot of products have gotten high enough that it makes sense for many applications where you need to combine a few basic functionalities, to make their own chips. Not all chips have to be your billion-gate 3nm node chips - there is a huge market for mixed-signal asics in the 180 to 22 nm nodes.

[@sovdee]

Mentor Graphics mentioned! I worked there this last year as an intern on parasitics extraction; it's such a cool industry.

[@michael_r]

I just started watching the video so I haven’t gotten to that part but when I saw the thumbnail my first thought was, “Shots fired, Mentor Graphics!” 🤣

[@dziban303]

parasite extraction? I usually just pinch the skin around the wound and the larva pops out

[@WooShell]

I've learned PCB design in the early 00's with Mentor Boardstation on a Sun workstation.. kinda sad that they got snarfed up in that huge duopoly.

[@jefefpv1695]

Now that Synopsys acquired Ansys who Acquired Ansoft, it would be nice to see that info added to this video.

[@stevebabiak6997]

That acquisition is not yet finalized. I believe that government antitrust approval is still pending.

[@ZeroToASICcourse]

Thanks for the shoutout Jon!

[@Nedski42YT]

I noticed that in this video and one of your earlier videos called "Designing Billions of Circuits with Code" you sometimes have screen captures of PCB layouts instead of IC layouts. I did PCB layout for about 30 years and used software from the same companies in your videos. I used software from Cadnetix, Orcad, PADS, Case Tech, ViewLogic, HyperLynx, and Mentor. The major difference between IC layout and PCB layout is the scale. IC's are in nanometers and PCB's are in millimeters. Have you considered doing a video about PCB EDA software and their history? Thanks.

[@ozne_2358]

I remember that in the second half of the 90s IBM had a EDA tool called "Build Gates".

[@brodriguez11000]

A play on...?

[@ozne_2358]

@@brodriguez11000Bill Gates

[@rehmsmeyer]

@@ozne_2358

[@rogerk6180]

I was just thinking about your videos today. A week without upload is rare for you! Good to see you are ok. Thank you for your amazing work, this has become one of my favorite channels across youtube.

[@williamhoodtn]

In the EDA world, don't forget about the Siemens Mentor tools. Not ASIC tools, but PCB development/simulation tools.

[@stuffstoconsider3516]

do they have a good market share?

[@williamhoodtn]

@@stuffstoconsider3516 Yes, huge!

[@michael_r]

The Mentor suite includes lots of IC design tools and yes they have market share, although smaller than synopsys and cadence.

[@stuffstoconsider3516]

@@michael_r Yeah, I checked and they aren't really bad. Market share in 2023 Synopsis 33%, Cadence 31% and Siemens 15%. These are the big three. Others are relatively insignificant. I heard that Huawei is working on theirs due to restrictions and can design microelectronics up to 14nm. They are trying to improve upon that.

[@JorenVaes]

@@stuffstoconsider3516 Huawei is not developing their own (though they do have some internal tools, as all huge companies do), but are working (and investing heavily in) Empyrean.

[@PhilippBlum]

0:17 What a timing and coincidence that Crowdstrike is on place 16.

[@Croz89]

Not for long!

[@PhilippBlum]

@@Croz89 true 🤣

[@ArnaudMEURET]

Hey look ! Crowdstrike used to be #16! 😅

[@ChrisJackson-js8rd]

i think the major synopsys advantage was that from a mostly functional input their software could output a structural design. Traditionally the translation from functional to structural had been done by highly skilled and well paid people. To be price competitive the other firms would have to trim their margins by whatever their customers were paying for this function internally + the cost of synopsys software, and could not compete with synopsys on a level field.

[@yds6268]

Tomorrow, I need to do a talk about our new education program to prepare (hopefully) future CAD and EDA software developers. So this video was a nice coincidence for me

[@PhilfreezeCH]

Are you using Yosys, OpenRoad and other open EDA tools for hand son exercises?

[@gregebert5544]

One big BIG thing that went on in the early ASIC world was that most foundries had their own set of tools for design-entry (usually schematics), netlisting, logic simulation, delay-prediction, timing analysis ( back-annotated delays into the logic simulator, as well as static timing analysis), and test-vector conversion. I personally worked with tools from LSI Logic, VLSI Technology, Toshiba, NEC, Mitsubishi, and probably others. Oh, what a horrible mess that was !!! Around the mid 1990s, the ASIC vendors realized it was too costly and inefficient to maintain their own tools, so they gravitated towards vendor-independent simulation tools, notably Verilog, Chronologic, Modelsim, and Vantage. There was also pressure from customers for the ASIC vendors to standardize the tools as well. Synopsys and Cadence began gobbling-up independent tool vendors.

[@atanumaulik7093]

Good to see that finally EDA companies are being fairly valued. The market behaviour is often strange. How can one justify a 3 Trillion dollar valuation for NVIDIA and only a few billion for EDA comapanies ? The former won't exist without the later.

[@SimonZerafa]

I do like your trolling pronunciation of Socrates. Bill and Ted would be proud 🥴👍

[@isaquejr]

Both Cadence and Synopsys started to build and sell IP using their own tools, that's a big change and a growing part of the revenue for both companies.

[@sellicott]

Ah yes, Cadence, the makers of software all chip designers love to hate. Software held together by lisp scripts and bubblegum, and the bubblegum is getting kind of old and brittle.

[@petertbbrett]

I agree, the Lisp is the best part. (I'm a software architect at Cadence, and I work on Virtuoso Schematic Editor).

[@BHBalast]

I don't design IC's but UI in their OrCad software for PCBs feels like 30 year codebase that is adapted to a new system every few years and was never refactored, everything works just like I wouldn't except it to work and is not intuitive. Also temporary trash files everywhere. Ewerywhere!

[@petertbbrett]

@@BHBalast More like 35 years old, but yes.

[@devanshudwivedi5875]

​@@petertbbrett could guys please update the GUI it's been the same for 14 years. Maybe add some snazzy animations

[@AdvantestInc]

Understanding the founding principles of ECAD and their differentiation strategies gives a new perspective on the competitive landscape of EDA software. Thanks for the deep dive!

[@muhdiversity7409]

The amount of damage Jack Welch and his disciples have done to so many industries is absolutely astounding. They all made off like pirates, though.

[@jimechols4347]

Yep he pioneered the traitorous manufacturing outsourcing that built-up other nations while destroying ours. Him followed by maybe the British.

[@brucekellett440]

Thanks!

[@kanyesouth9397]

Selling shovels is a good business in a gold rush

[@ChuckSwiger]

I got to play with an Intergraph setup with the digitizer tablet, for the backup hardware we were selling. The main disk was so small, our admin said it was mostly symlinks to the real files on another disk.

[@salsamancer]

Commenting before watching: i just want to say i love how wonderfully 90s the logos in the thumbnail are.

[@tomschmidt381]

Interesting timing, seeing CrowdStrike at #16

[@jimgolab536]

One of the coolest things that SDA tools could do in the mid/late 80’s was to let circuit designers write code to place and route polygons, wires, and transistors. This way, if you made some small change to a low level cell (like the location of an input node), you just reran the program and the layout changed. At the time, this was huge, because other groups in our company were still pushing polygons on Calma systems. Any little change could turn into a major relayout.

[@vincei4252]

7:35 LOL. I attended Middlesex Polytechnic (now University) in Bounds Green, London in the 80's studying Electronic Engineering probably when this ad was placed. The Bounds Green site was where the engineering departments were located and was a very futuristic building. The Bounds Green site was shuttered and I believe all engineering departments closed. Is a crying shame. As Asianometry was rattling off Sun and Silicon Graphics hardware I was thinking of all the Apollo workstations we had at the time which are listed on the Middlesex ad. Good times!

[@answerman9933]

So-crates? Not Sa-cra- tees? I guess Bill & Ted were correct.

[@michaelmoorrees3585]

Didn't pronounce de Geus properly either. The dutch "G" is next to impossible to pronounce by an English speaker. btw: Bill & Ted's Excellent Adventure is Keanu Reeve's best performance. That's including his Matrix & John Wick work.

[@gus473]

​@@michaelmoorrees3585Not "Point Break?" You're sure....? 🤔

[@jelleverest]

​@@michaelmoorrees3585the G was the least of the problem with that pronunciation lol

[@RahmanDwi]

Cadence is well-known by one of their designs like Xtensa that is used on ESP8266 and ESP32 microcontrollers

[@fcheung2888]

What changed? EDA design post 2016 must include (both at device level and at package level) physical parametrization as part of the design in many applications. Some growth to occur as a result.

[@markpoulsen6429]

Was thinking "that's not how you pronounce de Geus", when you hit me with the So-crates. Excellent!

[@mrhassell]

Pronounced, like the Greek of ancient renown, SOCRATES is a system designed to automatically synthesize and optimize combinational logic circuits from Boolean equations. It uses Boolean and algebraic minimization techniques to optimize the logic, and further optimizes the resulting circuits using a rule-based expert system tailored to user-defined technology. This system was presented at the 23rd ACM/IEEE Design Automation Conference in 1986. It presented a significant development in the field of electronic design automation, helping to streamline the process of creating efficient logic circuits.

[@rb8049]

And the software is based upon code dating back to punch cards.

[@stephenjohnson3591]

Duopoly? I thought it was Synopsys, Cadence, and Siemens EDA (Mentor) in that order. Used to be the big 3, not 2. Has market share decreased that much since Siemens bought Mentor and Calibre along with it?

[@tomenglishmusic6808]

Outstanding as always. EDA has been a duopoly my entire career so far (since ~2000) and is so stagnant young folks no longer see chip design as an attractive career. Tools and flows have not changed radically in the last 20 years. Starting a new company in chip design is almost impossible due to prohibitive EDA licence costs which scare away innovation. The industry is ripe for total disruption, but how?

[@policedog4030]

Expiring patents?

[@JameBlack]

Chinese domestic eda

[@MrCalls1]

I wonder is there a diagram of a smart phone/laptop/pc/server showing ever way it flows from a silicon mine? And all the steps along the way? Because I’ve been watching and enjoying this channel for a while and I find it so easy to get lost at where in the dependency chain we are, and when we are providing a service that actually interacts with 3 different layers and chains.

[@lensiax9276]

I worked briefly in the process design kit team (the people who manage the EDA tools, the LVS rules, the DRC rules, etc) for a big defense company. Our team serviced all the designers using our foundry and was about 10 people. The average employee age was about 50 to 65 years old, lol. With lots of very special semiconductor technology types, we had to create some wild PDKs. While I personally thought at the time PDK was a little boring, it widened my eyes as to a) the significance of this technology and its prospects in the future and b) where the wealth in a semiconductor company truly exists. A good PDK is worth its weight in gold.

[@LayouteditorNet]

Oops, I'm surprised to see something from my website here with a source citation 😳😊

[@jaymacpherson8167]

What EDA software was the leader for cell phone circuit designs in the 1990s and 2000s? At the time cell phones ran at much high frequencies than CPUs, GPUs, and motherboards.

[@michael_r]

Synopsys and Cadence. When you say “much higher frequency”, I think you’re talking about the RF and not the logic circuits.

[@jaymacpherson8167]

@@michael_r oops, good point. The question remains…. Who was the leader? It wasn’t Cadence or Synopsys.

[@michael_r]

@@jaymacpherson8167 yes it was. I worked in semiconductors in the late 90’s through mid 2000’s. The largest EDA vendors were Cadence and Synopsys. Mentor also had significant market share. There were more niche players - Magma, Calibre, IKOS, probably a bunch of other companies I’m not thinking off of the top of my head. But Cadence, Synopsys, and Mentor were the big names for large gate count ICs, at least in the ASIC and SOC world where I worked.

[@jaymacpherson8167]

@@michael_r Yes, Cadence was the big dog for the larger market. When it came to cell phone design for high frequency RF, the EDA software of choice was ADS at HP. Tho they spun it off in Agilent, who sold it to Insight. I don’t think it has cache anymore.

[@markwilliamson9199]

Gosh I used Bell to develop my VLSI student project in 1985, took hours to generate a net list on a VAX :-)

[@q45ij54q]

Nice video. A recommendation for a future video would be the Cadence/Avanti/Synopsys lawsuit that eventually led to Synopsys getting a foot in the APR door.

[@normalizedaudio2481]

There is Mentor Graphics too.

[@T3hderk87]

Thank you sir, as always food for thought!

[@robertpearson8546]

I worked at Texas Idiots in 1978. VLSI was new. Clock speeds were 10 MHz. And logic gates were TTL. I worked on the I²L SBP9900. I had to create libraries so TTL designers could create I²L ships. EDA restricts designers to 1968 CMOS. State of the art is 5 GHz at 300 W. If you used resonant tunnel diode threshold logic you would be at 33 THz at 5 W. All the EDA software could have to be rewritten.

[@miyatenmeiritsu1810]

I'm curious what kind of EDA that companies in China (like Tsinghua University, Huawei and SMIC) uses. Considering that these EDAs were US companies, they would most likely barred from using those EDAs in official capacity. Maybe whatever alternatives they had were way behind the three EDA giants (or not), but either way, I'm looking forward for that video.

[@RevolutionEDA]

This is why Revolution EDA exists. It aims to disrupt the status quo in custom IC design software with generative AI enabled software.

[@BHBalast]

Thanks for the info, I'v never heard of it

[@meneldal]

Not to go against your statement about Cadence being more popular in Japan overall, but the place I work at uses both depending on the project, typically based on what the client wants. I have mostly used synopsys tools but since most stuff is standardized now switching between the tools isn't as bad as it could be. And I'll say both do have a lot of potential growth potential for the IDE side, especially for anything that isn't a toy project, usability for real world stuff large scale SoCs where you need to deal with pesky things like some parts being shipped encrypted (as clients don't want you to see the insides), it gets pretty annoying.

[@KeviPegoraro]

when at 8:20 you do reconize Bob before reading, is because you saw too much Asionometry already, just like me

[@bmw128racer]

I used VALID SCALD System hardware during my days at Hughes Aircraft. Hughes used Daisy Mega Logician hardware as well.

[@geographicaloddity2]

Thank for describing Jack Welch as an over rated CEO. I think I would go one step further and call him a ruthless, greedy sociopath, but that's just me.

[@jimgolab536]

And me.

[@Confucius_Says...]

And you would be right.

[@dogaarmangil]

9:16 how to pronounce "aforementioned": uh-FAWR-men-shuhnd (4 syllables) "uh" as in "above" + "FAWR" as in "horse" + "men" as in "men" + "shuhnd" as in "shun"

[@AndrewHelgeCox]

0:49 the cell libraries contain much more than just gates.

[@ahmedhassan9485]

It's mainly the covid the drove the stock market crazy for those 2 stocks. Until 2019, Synopsys Market Cap was around 20 B$ and by 2022 It rose to around 60B$

[@TheAnimeist]

Reasons for the growth of Synopsys and Cadence in 2016-2017: Not sure of this, but perhaps their accusations had fallen into their frameworks by then - so they were ready Smaller processes (10 nm, 7 nm, 5 nm) - dictated the need for these tools Growing market - high chip demand - IoT, SoC Their subscription/licensing model changes may have something to do with it as well - this did make all of their tools more accessible once you got a license.

[@courtney2394]

Hi really interesting comment. What were the changes to the revenue model? What was it before and anywhere good I can read about this? Thanks

[@matthewmnorman]

I think the name of de Geus’s system might be mispronounced. Not sure how he’d say it, but usually that word is read “sock creh tease” like the philosopher. 9:48

[@Asianometry]

It’s a callback to Bill and Ted’s Excellent Adventure

[@matthewmnorman]

@@Asianometry 😂👍🏼

[@Jeremy-fl2xt]

@@Asianometry "Like sands of the hourglass, so are the days of our lives." - Socrates (he's under so'crates)

[@dalecomer5951]

​@@AsianometryWhy don't you pin this comment?

[@YolandaPlayne]

2017 was early scaled Ai. Earlier Ai was an industry secret for about a 30 years at that point, having invented such products as the cross-bristled toothbrush. These were called expert systems but used evolutionary-evolved neural networks.

[@SeanPannella]

I use Mentor’s ModelSim and Cadence Xcelium

[@ailivac]

0:20 I have a feeling Workday is about to be bumped up to number 16 on that list!

[@thoselog]

A+ work as usual.

[@Kato0909]

Any news video planned about reported copper interconnect vias oxidation in Intel 13th and 14th gen CPUs (Intel 7™, or previously called 10nm SuperFin lithography)?

[@benjaminlynch9958]

That is just a theory at this point and hasn’t been confirmed (although it does make sense). But I too would love to see this channel address those rumors. His expertise in this area is second to none on the KZbin platform, and any insights would be a huge value-add to the community.

[@TheParadoxy]

Really interested to see Intel's next gen because it's supposed to be their first architecture using "industry standard EDA". If it turns out that all or most of Intel's design oversights are resolved by using Cadence or Synopsis, that will be big news

[@meneldal]

@@TheParadoxy The software isn't magic, you still have to use it correctly. It takes years before you can get experienced enough to not let potential bugs through. Depending on how different their pipeline is, it could take a while to adjust. For example you typically want stuff like 100% coverage of your blocks, but in practice, even with some convoluted tests, some bits aren't getting to flip or only one way around, and since you don't want to just force the signals to change since that defeats the point, you make exclusion lists of stuff that can be ignored. It's very easy to get those wrong and miss a signal that isn't connected properly. It happens easily if you have a block that you reuse between projects and you don't use a feature in a project.

[@TheParadoxy]

@@meneldal thanks, I appreciate your response. Does this mean you expect Intel to struggle even more since they're changing to a new design flow?

[@meneldal]

@@TheParadoxy It's really hard to tell. Intel has plenty of great talent, and I don't doubt they have plenty who are experienced with other tools than the ones they currently use. Not to mention CPU verification is a very different job from SoC verification. Typically we use ARM CPUs and if we encounter a bug, a problem in the design from ARM is usually the last possibility on our list, below asking Cadence/Synopsys (which we do every so often because we can run into weird edge cases of hardware language specs, but I don't recall the last time we had to give a bug report to ARM, even if we do ask for stuff because we aren't sure about the spec sometimes). Having to assume the CPU can do something stupid would definitely up the complexity of my job by a huge factor.

[@usercurious]

0:15 Shout to CrowdStrike 😎😎

[@drachamberlain]

So what was first, the hardware or the software?

[@kije6639]

The screenshot in the first image showed crowdstrike pre-windows crash lol.

[@jbdawinna9910]

You’re awesome, great video

[@alexandresen247]

your pronunciation of socrates is impeccable, dude

[@mattbland2380]

Another excellent video.

[@tomholroyd7519]

19:27 It was deep learning on GPUs

[@nesseihtgnay9419]

"wife, get up its Asianometry"

[@Michael_Brock]

Would be interesting how eda duopoly line in with the fabrication foundries. Only viable now TSMC and Samsung. Intel is 5 years behind and losses a year every year. China (PRC) ten years behind. But PRC are making progress. Intel has been stuck for 6 years. Stuck not progressing.

[@benjaminlynch9958]

There’s a lot more fabs than just Intel, TSMC, and Samsung. Semiconductors are a lot more than the leading edge, and also more than just x86 or Arm chips. Texas Instruments UMC SMIC Micron Analog Devices Rohm (formerly Lapis) Fuji Fujitsu Cannon Kioxia SK Hynix Sony (yes! Even Sony!) NXP Global Foundries All of these companies currently operate fabs. Some for memory. Some for MEMS or analog chips. Some for the defense and aerospace industry which tends to use very old process nodes but which also has additional design requirements (eg able to withstand repeated high-g stresses and solar radiation).

[@Shivansh_singh4539]

Hello sir, I am Shivansh from Saharanpur, Uttar Pradesh. I have been following your content for 6 months now, and I believe your subscriber count has grown significantly in that time. I have also commented on your videos, if you've noticed. I have watched your videos like "My Fav.," semicondutor shortage " and "tsmc history," etc. I understand that your team is currently short-staffed and the competition is tough. I've observed that while short videos and reels are popular, but you predominantly create long content , which is commendable. Your channel is growing, and I have faith in its continued growth. So I am interested in joining your team. I can contribute to content writing , because I love technology so I have also many stories of india . Or I can make video in hindi because hindi people is large and your should gain more and more subscribers and Indians also learn about how technology formed and pioneer behind thise technology . I can also manage social media . Make contents . I can also help in subtitle making job . Regardless of your response, I must say you are the best teacher I have ever seen on KZbin. 😊

[@Shivansh_singh4539]

So any reply

[@alfredfuchs5615]

What happened? IMHO AI happened. Instead of preparing for a mature market at the end of Moore’s law suddenly there was a new gold-rush into all kinds of massive-parallel computing architectures i.e. novelty that unseated the Intel paradigm. And EUV made further miniaturization feasible. The geostrategic relevance gave their customers access to deep pockets and coverage against risk of failure. Ok, that’s a guess without knowing the sales structure. I doubt that Siemens is doing well in this end-game strategy.

[@williambrasky3891]

Was that a Bill & Ted joke? So Crates!!!

[@BobSmith-wi4dv]

Hol up what was that original namw?

[@policedog4030]

Indirectly but thanks to your video i just found this book from the inventor of the MOS, CCD, first commercial microprocessor, etc. Strangely he has no Nobel prize as of yet, but seems to me he should have that. Silicon From the Invention of the Microprocessor to the New Science of Consciousness By: Federico Faggin Narrated by: Mark Bramhall Length: 9 hrs and 46 mins Unabridged Audiobook Release date: 03-09-21 Language: English Publisher: Waterside Productions, Inc.

[@jimurrata6785]

Rubylith, Oh! 70's me still has calluses from swivel knives and dental picks...

[@elizabethwinsor-strumpetqueen]

sock crate tees - he knew it ...he's messing with us !

[@KawekSL]

Picture with stocks not up to date, i'm sure CrowdStrike is going down :P

[@thirstyCactus]

should "so-crates" be pronounced "sock-rat-teas"?

[@ntabile]

Should that be Sock-ra- test?

[@umeng2002]

Do you do anything other than regurgitate wikipedia information? Do you have any degree in EE? Are you just a history major?

[@MathematicsStudent]

It's rather frustrating to see so many comments complaining about the pronunciation of "Socrates", when Asianometry has confirmed here that it was a joke and a reference to the famous 1989 movie "Bill and Ted's Excellent Adventure".

[@MathematicsStudent]

@thePronto He replied to one of the many comments here that complain about the pronunciation of Socrates.

[@TheGreatAtario]

Were it a reference, you'd think there would be some indication of this in the video

[@dalecomer5951]

If so that comment should have been pinned.

[@MathematicsStudent]

@@TheGreatAtario A lot of people understood the reference, as can be seen in this comment section... Also, jokes do not always need to be explained. In this case, the pronunciation of "Socrates" is so universally known among native speakers of English (which Asianometry is) that you shouldn't have to point out that it's a joke, like a lot of the mispronunciations are on this channel.

[@TheGreatAtario]

@@MathematicsStudent There's a word for jokes that are indistinguishable from ordinary mistakes. Also, I have severe doubts about that "native speaker" bit

[@PaulJurczak]

Socrates is not pronounced as sock-rates, but as saa·kruh·teez. It is a name of a notable Greek philosopher: en.wikipedia.org/wiki/Socrates

[@darklordzqwerty]

Where does altium land in this arena? It's used by so many companies.

[@slicer95]

Altium is board design . Synopsys amd Cadence focus on chip design.

[@darklordzqwerty]

@@slicer95 ahhhhh this video focuses on silicon only. I thought they were talking about cadence as a whole because cadence allegro and orcad have a damn chokehold on the pcb industry its crazy.

[@michaelm358]

Pls define upftont what EDA stands for, to save us looking it up

[@PRAIRIEGH0ST]

You used to have somewhere subscribers could review your sources, is that still around?

[@atanumaulik7093]

Another of significant tech chokepoints. Increadsing focus of US export controls.

[@paulgush]

EDA = electronic design automation

[@DimasFajar-ns4vb]

peace be upon you sir and zamzam water

[@mrmiliman]

Aren't FPGA companies like Xilinx (AMD) and Altera (Intel) technically consider EDA vedors?

[@TeeTeeNet]

Why you using black and white pictures for 1989?? like they had colour back then. Colour TV came to the US in 1953ish

[@kushyglowy8409]

Incredible

[@crashdavis4123]

of course there's a program that actually places the transistors for you, and of course it's a program that hasn't changed in 30 years. engineering

[@vvvorlds]

Maybe a short video about intel problem

[@hardchipgame]

But did you hear about EDWA or Electronic Design Without Automation software?! Like Hard Chip on Steam ?! (this is joke but I though this was a very interesting video, and my brain made the link automatically)

[@stevegunderson2392]

Miss pronouncing De Gues classic! RTL is the language used in synthesis. I have come to the conclusion that you do not actually talk to people in the know. TI is the father of DRC checkers. You completely ignore Mentor graphics and the fact that no one uses Cadence for DRC checking, Mentor dominates that.

[@niktak1114]

Duopoly? Calibre would like a word...

[@OperationXX1]

@@niktak1114 unfortunately, Mentor isn’t a tier 1 EDA vendor, it doesn’t offer a competitive comprehensive solution for leading edge chip design. To do leading edge chip design buying tools from either Cadence or Synopsys is a must but buying Mentor tools is optional/complementary. So, yes it’s a duopoly.

[@sailorbob74133]

What about Nvidia's cuLitho?