Clock divided by 3 with 75% Duty Cycle.

[@poojithaborra1650]

This was really useful. Clear explanation.

[@KarthikVippala]

Namaskaram poojitha🙏 , thanks for the support, good luck & great health 👍😊 take care.

[@Unpredictable110]

Thank you bro , clear explanation ❤

[@Rcs9060]

Here how multiplier will works internally, you have showned block diagram, how hardware can implement here? request to do the videos on clock multiplier by 2, later by 1.5 2.5 3 3.5 etc

[@KarthikVippala]

Sure

[@RAJASEKHARPULLAPANTHULA]

the wave form at 10:34 looks like clk/2...please correct me?

[@andrewmicro16123]

Question, would this possible create a glitch on the position where one 1/3 divider output is falling while the other is rising?

[@rrt9596]

Clear explanation. Can you start a series on SystemVerilog?

[@KarthikVippala]

Hey Raj , thanks for your feedback , Yup I will start system verilog after 2 months , because I will cover basics , & verilog first👍 pls stick on till then

[@rrt9596]

Karthik Vippala Thank you! Yes, Verilog is essential to cover the basics. Also, can you make a video on Crystal Oscillator?

[@KarthikVippala]

@@rrt9596 hey thanks for replying back , yup I will do a video on crystal oscillator , but can I know what is that you most need in it.

[@rrt9596]

Karthik Vippala I want to understand how exactly electrical signal with precise frequency is generated by crystal. And, how it is used in current times and what is the future of it? I really appreciate your efforts :)

[@esw123rag]

How did you designed that circuit . How did you get the thought of giving 2x clk

[@KarthikVippala]

Hey Raghu , thanks for asking, I reverse engineered it , I started from output signal and worked backup to input signal. I hope this helps you. If you have any questions please feel free to comment. I am happy to help you 👍

[@KarthikVippala]

Hey vikas kumar, thanks for asking. I have explained about clock divided by 3 in seperate , check it out in my channel . If you have any questions please feel free to comment, I am happy to help you 👍

[@vatsala900]

@@KarthikVippala pls explain f×2 circuit in separate vedio ... Remaining i understood very well ...

[@KarthikVippala]

Frequency and time period are reciprocal to each other. So we need to reduce time period for increasing the frequency.

[@priyankasingla3609]

Can you make a video for mod 5 ,7 with 50% duty cycle

[@mahinvikeshn.k2249]

cant we just complement the Q0 from the mod 3 counter to obtain this result

[@sandeep_shetty]

What is multiplier used for f/4 with 12.5 duty cycle

[@KarthikVippala]

Hey Sandeep , here I have reverse engineered from output to input , if you do that that you might get it. There is no short method for it . Good luck, good health 👍

[@rahularora4409]

PLEASE TELL ABOUT 66.66% AND 33.33% CIRCUIT DIAGRAM INPLEMENTATION FOR MOD 5 AND MOD7?

[@KarthikVippala]

Will make a video on them, thanks for asking

[@doganatlas3369]

Some feedback for the future. The background music is annoying. You do not need it...

[@KarthikVippala]

Thanks for the feedback, will include it in upcoming videos. 🙏

[@lijijoy22]

how to design a 60% duty cycle with T=1 ms from 100Mhz clock frequency??

[@naliniscookerycorner1894]

How to get 12.5% duty cycle ?

[@KarthikVippala]

1/8 of cycle,is 12.5 % duty cycle, try reverse engineering , start by drawing the output , then think how can we implement it with know logic . Good luck, good health 👍😊

[@ruzubergaming9442]

How to get 55.55% and 77.77% duty cycle

[@uk4725]

For the love of God, stop that fake accent.

[@KarthikVippala]

Improving on it

[@uk4725]

​@@KarthikVippala Why do you pathetic people feel the need to fake a western accent?