Toggle synchronizer Explained!! Why 2 flop synchronizers cannot synchronize a pulse? | CDC

[@jayparekh9768]

Nice video Man..Kudos! Two things to remember.. 1) You can't pass pulse faithfully from fast to slow using 2FF synchroniser 2) convert pulse to level in sending domain and then again create pulse from level in receiver domain

[@KarthikVippala]

Thanks for the summary 😊🙏

[@onkardesai30]

Nice video! but QA will be sampled as soon as (+propagation delay) the positive edge of CLKA comes. In video, it is sampled on the next cycle which is not correct.

[@ankitsingh-wg3cn]

yes, but in the video, its not sampling time, its the sampled output Qa shown in diag which will be once cycle delayed.

[@tuhinkarak4927]

Really Really Nice Video Man........I have seen many videos of FIFO, but this one cleared all my doubts.... Kudos man

[@real4788]

output of Q1 is wrong. It should be 1 as soon as there is posedge clock. In your timing diagrams, there is 1 clock period delay

[@sanjeevyadav-lw4ky]

yes

[@BonBonShrimp]

Nice video. I think it needs to be mentioned that if clkA is generating more than one pulse, the gap between them should be at least 2 clkB cycles wide (if using a 2-stage synchronizer).

[@ankitsingh-wg3cn]

it will work in case of 1010 also.

[@InterestingTopics2103]

Well explained...only issue is Q is modified at next edge instead of present edge in timing diagrams

[@KarthikVippala]

Namaskaram 🙏 Manoj Kumar , thanks for the support , thanks for pointing, good luck & great health 👍😊

[@krishvamsi9787]

why it should modified at present edge..?? can u plz ans me..

[@InterestingTopics2103]

@@krishvamsi9787 that's basic thing bro....any flip flop will capture the data at its input if data is ready at it's active edge

[@trilokjt2118]

Hey Karthik, great video. Keep doing good work 👍

[@KarthikVippala]

Thanks for the support brother 👊

[@tyogarasa]

Great video. Thank you!

[@KarthikVippala]

Your welcome ☺

[@zohaibisrunning]

what is the constraint on input that must be respected by the sender for the toggle synchronizer to work?

[@prabhustocks5992]

Why would Qa take an additional cycle to go to 1 post the INPUT and CLK A going high. It should go high in the same cycle.

[@roshanekre959]

Thankyou sir Can we use or gate instead of mux 2x1

[@KarthikVippala]

Yes

[@Shrawankumar-oc2vj]

Thank you

[@krishvamsi9787]

is toggle synchronisation works only for single bit ?or can we use this technique for multiple bits ?

[@ankitasharma9841]

How will the signal Qb come out of the metastable state on its own ?

[@uday5786]

excellent explanation

[@KarthikVippala]

Glad you liked it!

[@rajuchintapatla2881]

Sir, in every case, you have taken the correct logic level after the flipflop came from a metastable state, but it's not true in every case, right? Because when a flipflop comes from a metastable state it can take either zero or 1, if we get the wrong stable state, then total functionality changed? then what is its use?

[@kedharguhan]

Great topic and video, thanks! In practice, is this technique more useful in the ASIC domain or in the FPGA designs? Or is this equally used in both?

[@AdrianoLeszkowicz]

Tks , great video Something you miss : what will help if the pulse is too long ( i.e. more than 1 clock period ) , also what about consecutive pulses ( that must be limited by the slower clock )

[@KarthikVippala]

Namaste Adriano 🙏 , I have covered it next video , please check it out in CDC playlist of my channel, thanks for watching and the suggestion , good luck & great health 👍😊

[@OneKyox]

Is the mux functionality not the same as a T-FlipFlop?

[@akshayraj.amudala708]

When input is back to 0 from 1 , Qa will again change to 0 right. How is it still 1.?

[@RajeevKumaryadav24]

which case it is used: 1.Pulse going from high to low 2. pulse going from low to high 3. Both case

[@KarthikVippala]

Hey Rajeev thanks for asking, Yes we can use it for both cases . Good luck, good health 👍

[@ankushchavhan3382]

Nicely explained, can we use xor gate instead of a mux, where 1 input is q and other input is pulse.

[@KarthikVippala]

Namaskaram Ankush 🙏, thanks for asking, you can use it , mux is universal gate any gate can be formed. Good luck & great health 👍😊 take care.

[@vivekkumarbharti6633]

Hi Karthik, thanks for great explanation Does it possible that pulse can be generated by noice?

[@vivekkumarbharti6633]

Just asking 😉 i am noob here.

[@KarthikVippala]

Didn't get u , can you elaborate 👍

[@bhuvskaya8898]

Can we use this for array / data synchroniser? Fast to Slow clock sampling

[@kaustubhrajvaidya6355]

Hi Karthik, Nice explaination. One doubt what if the output of Qb settles at 0 instead of 1 in that case we wont see any pulse , is this correct understanding? in that case pulse will be lost . Or do we have always "assume" that Qb will settle at 1 only.

[@dipenjivani2619]

If Qb is not settled with '1' in first cycle then no worry as it will be settle with '1' in next cycle as it's input QA level is set to '1' and its continue to '1'

[@venkatm5443]

What happens if source flop is reset but destination is not ..the latched signal will toggle and destination will detect erroneous pulse

[@KarthikVippala]

Yes Venkat , you are correct both need to be reset at same time

[@uday5786]

thanks for video

[@KarthikVippala]

Thank you for your feedback 👍

[@vijayshreeadhikari3989]

The pulse we transmit from clock domain A is of 10 ns but what we receive at clock domain B is of 20 ns .But it should be of 10 ns ideally .How to resolve this?

[@KarthikVippala]

Namaste Vijayshree 🙏, it's moving from fast clock to slow Clock , we can use fifo to synchronise the domain crossing and depth will be calculated accordingly, thanks for asking good luck and great health 👍😊

[@abhijitkumar5696]

when qa is initially 1 , then design wont work?

[@hrishikesh97]

hello, I have a doubt. @8:45 time, Why is Qc not capturing metastability glitch from QB?

[@ankitamohanty199]

This is bcoz the output at qB has already got stabilised, i.e. it does not violate the setup time of f/f C

[@KarthikVippala]

Namaskarm Ankita, . Thanks for Commenting , good luck & great health, Take care :)

[@ankitasharma9841]

Hi Can you also make some video on how to calculate FIFO buffer depth.

[@KarthikVippala]

Namaskarm Ankita, Kindly checkout my channel ,I have discussed on how to calculate depth of FIFO. Thanks for the asking , good luck & great health, Take care :)

[@uday5786]

why the delay of first flip flop u have taken is one clock period

[@KarthikVippala]

Delay can be considered or may not be considered , it depends on when then the mux output arrives ,it won't be a issue even if you start a clock period ahead .

[@kritijaiswal4219]

What is another technique to transfer multibit data in asynchronous clock domain apart from FIFO? IF tha data is changing frequently

[@KarthikVippala]

Hey kirti, thanks for asking the question. Handshake synchronization, mux synchronization are some other techniques which I know. You can check them out in my channel , name of playlist clock domain crossing. If you have any questions please feel free to comment 👍

[@kritijaiswal4219]

@@KarthikVippalaHey thanks for replying. yes but these techniques have greater latency than FIFO and also they are not suitable if the data is changing frequently.

[@KarthikVippala]

@@kritijaiswal4219 Yes ,latency is high, this methods can be used when there is shortage of area and data must not change so frequently. FIFO is best method for CDC if requirements are met, as per my knowledge.

[@kritijaiswal4219]

@@KarthikVippala okay, thankyou Karthik

[@KarthikVippala]

Your welcome, good luck 👍

[@shaikon5617]

Instead of "Why 2 flop synchronizers cannot synchronize a pulse" - A more accurate statement would be. "In order to synchronize correctly with 2 DFFs - the Nyquist criteria must be satisfied"

[@ManishKumar-pl3dq]

I feel output of Q1 is wrong it will be one clock before @ time(1.24),,,,,,,,well rest thing nicely explained

[@kishandubal211]

how will it give single pulse ? i think it will give 2 pulses over o/p because of xor.

[@KarthikVippala]

Hey kishan thanks for asking, here o/p will give single pulse only not two pulse , please check it once again 👍

[@kishandubal6709]

@@KarthikVippala So, here whenever b2 is high at the same time b3 is low. So, one pulse o/p over it. Now the same pulse comes to b3, that time b2 will be low, so again another pulse will come to output. So, definitely it will give 2 pulse. By the way method is useful for single bit to streach as level with higher to lower freq synch.

[@KarthikVippala]

Hey kishan you are correct if b2, b3 gets low but here we may not make them low again.

[@kishandubal211]

@@KarthikVippala ok. but it doesnt matter if requires to make it as low or not. in any case it will give 2 pulses. i think xor is not required. it can take output from b2 or b3 flop as per latency requirement.

[@KarthikVippala]

Thanks for asking , good luck brother 👊

[@gauravshukla9452]

1)how to detect back to back pulse? 2) if my pulse width in source clock domain is N*src_clk_period. then how to generate pulse in destination clock domain of N*dst_clk_domain?

[@gym_monk6822]

y Qa ll capture i/p after 1 clk cycle . i sud capture the ip asa it sees a posedge isnt it?

[@shilpa4600]

Hi Karthik, When does this level will go to low? once it detects pulse, it is becoming level and then stay as continuous level, what if we want to synchronize another pulse which is coming much later than first pulse? in that case we need to make the level to zero at some point to re-initiate the next pulse synchronization. Pls suggest.

[@KarthikVippala]

Pls check out clock domain crossing playlist in my channel , in that pls watch handshake synchronizer , it is used for the issue you asked. Good luck, good health 👍

[@shilpa4600]

@@KarthikVippala Thank you so much.

[@shilpa4600]

Hi Karthik, in the handshake based pulse synchronizer, u have explained when multiple pulses to be synchronized, but the input pulse is getting controlled by busy signal. Here my question is, if we don't have control over input pulse generation ( multiple pulses getting generated , and if we have enough clocks to synchronize them). in that case how do we make the level low, so that next pulse can be initiated for synchronization.

[@KarthikVippala]

There is one restriction in pulse synchronizer that back to back (one clock gap) pulses cannot be handled. To make sure the next generated pulse in source clock domain gets definitely transferred and synchronized in the destination clock domain, the handshake based pulse synchronizer generates a “Busy” signal by ORing A1 and A3 flip-flop outputs. Thus the logic generating the pulse shall not generate another pulse till the busy signal is asserted. Thanks for asking the question, good luck, good health 👍😊, excuse me I missed the question ,since there is no notification for new comments in old comment , please do comment newly when you want to ask👍

[@abhijitkumar5696]

@@KarthikVippala His question is regarding toggle synchronizer asking when will the level go back to 0 to synchronize next pulse

[@uday5786]

can u do on handshake pulse synchronizer and fifo synchronization

[@KarthikVippala]

Yes , but need some time 🙏

[@KarthikVippala]

Hey uday I have done a video on asynchronous FIFO , pls check it out , there is synchronization in it.👍

[@uday5786]

@@KarthikVippala can you do it before Friday..as I have seminar on that topic on Friday..plz

[@KarthikVippala]

Ok , I can do handshake pulse synchronizer , but for FIFO please refer this link below kzbin.info/www/bejne/Zn25eYOIos5rbsU

[@KarthikVippala]

Hey uday , sorry man I can't do the video before or on Friday 🙏 , I have some personal work , hope you understand , need some more time .

[@rajavardhanreddyg3360]

How to synchronize if pulses are coming back to back? Could you please explain ?

[@KarthikVippala]

Hey Rajavardhan ,thank you so much for asking the question . Now coming to the explanation , since you said two pulses are back to back ie there is clock period between two pulses. I am explaining this on circuit shown in the video ie flops A,B,C,D and QA,QB,QC, QD as respective outputs. When circuits see the first pulse the we will get a high at QA , when second pulse is seen then QA will be toggled QA will be a level of two clock period . At QB we will have a metastability , this will settle after certain time and passed to QC , QC will be similar to QA and that is passed to D FLOP and we will get QD which is delayed version of QC . Now we will XOR QC and QD we will get our pulses back .

[@KarthikVippala]

_________________________ QC _____________________| |_______________________ _________________________ QD ____________________________________| |_______________________ hey rajavardhan thank you once again for asking the question , please stay connected by smashing that subscribe button and I hope this clear's your doubt.

[@rajavardhanreddyg3360]

Karthik Vippala Thank you for the clear explanation.pls make videos on mux Synchronizer and handshake Synchronizer also

[@KarthikVippala]

@@rajavardhanreddyg3360 Thank you for replying back , for sure I will make videos on other synchronizers too 🙏👍 but need some time 🤗

[@KarthikVippala]

@@vivekvashisht3190 Hey Vivek thanks for asking the question , now coming to explaination , If we have that slow clock that if 4 times slower ,then we can delay the the level and perform an OR operation so that other clock can see the signal at posedge . This is a practical approach , for this case we need to carefully analyze the timing and then need to design. This explanation is kinda rough , but hope you pick what you need . Thanks for asking 👍

[@PradeepSingh-kp6tu]

the pulse width is increased here at ouptut

[@sanamkala8795]

Hi Karthik, If I use T-FF instead of mux and D-FF, will it be ok?

[@ankitsingh-wg3cn]

yes, it will work

[@gauravsoni91]

How to synchronize when multiple pulses come?

[@KarthikVippala]

Gourav Soni hey thanks for asking the question. If we have many pulses in our design to synchronise we use handshake synchronise to avoid metastability . Check out handshake synchronizer in my playlists of synchronizer , if that doesn't clears your doubt , feel free to ask 👍

[@bobbiliraghuvenkatanaresh7599]

Give hdl code for this implementation

[@KarthikVippala]

Sure will cover in later video's , thanks for asking, good luck and great health 👍😊