ClockDomainCrossing

[@paulfranzon2229]

W Caleb: C and D can be different. They both change on the rising edge of the clock, with D taking on C just before the rising edge and C taking on B from just before the rising edge. (slide 6). Muddu: To compensate for that situation the controllers on slide 9 will detect when the FIFO is close to being full, not just the instant its full. The writing will stop in sufficient time then.

[@wcaleb5891]

Hi Dr. Franzon, could you please explain how the solution for the repeated value appearing in C? Every posedge clock (I assume that this clock is clock1 of the sending side), D gets the value from C so that D and C will hold the same value. Therefore, Assign change = (C!=D) would always have change=0. You mentioned that the assign operation happens at the second FF. I am not very sure how does the code show that it happens at the second FF and how there might be a case that D and C would be different.

[@msapreek1]

same question.. if both the flops capture data correct then destination domain will have same data capturing in two cycles..

[@mudduharikrishna8847]

Hello Dr. Paul Franzon. Nice lecture on FIFO. However, I have a question. In the FIFO design, to compare the rptr and wptr, you are feeding one signal into another clock domain. The rptr which is coming from the slow clock domain to faster one can be synchronized with sync Flip-flop logic explained in the beginning. However, the wptr which is coming from fast clock domain to slower clock domain and it cannot be synchronized as per the condition mentioned @ 7:42. How is the problem solved? Thank you in advance.

[@paulfranzon2229]

This is why it uses grade scale encoding and a full/empty criteria that permits two empty slots.

[@varshapatel5361]

Paul Franzon grade scale is another name for grey encoding? @ 18:09 you may want to change typo (I think) of Asynchronous FIFO suggestion for Fast to slow instead of slow to fast.

[@carterlee287]

When we implement Asynchronous/Synchronous FIFO, What timing design constraints do we need?

[@paulfranzon2229]

Just the conventional timing constraints in each clock domain as per the synthesis script. No additional constraints are needed. You need to either guarantee the FIFO wont overflow or do something on overflow.

[@HDgaming345]

If the two clocks are source from the same PLL do we still need an asynchronous FIFO or a simple shift register would be enough?

[@paulfranzon2229]

The edges of the two clocks are still uncorrelated so a multiflop resynchronizer is enough.

[@vazgengyoletsyan3933]

please show reference links

[@babatundetaiwo2817]

"When the two clocks are "Roughly" the same" What do you mean by this?

[@paulfranzon2229]

The two clocks are different but not different enough to simply use two flops in a slow to fast crossing.

[@babatundetaiwo2817]

@@paulfranzon2229 okay so you mean the two clocks have different frequencies. One may be slightly faster than the other but not fast enough for a slow to fast double flip flop implementation.

[@paulfranzon2229]

Yes. I am assuming you are referring to the conclusions.