Designing a First In First Out (FIFO) in Verilog

[@anupammathur17]

In my opinion at 23:30 , fork-join would be a better option to execute if conditions for both Head and Tail pointers simultaneously. Otherwise the compiler might execute the first if-else block first and then the second if-else block.

[@vinayakvakare9836]

simple and clear explanation , extremely helpful

[@mcb6331]

Very simple but informative video.

[@vcubeful]

rd_ptr and wr_ptr shouldn’t be of 6 bits to count till 64, with this example max value of rd_ptr and wr_ptr can go up to 16. Please correct me if I am mistaken here.

[@manishsrivastav4897]

whom you are explaining 😂

[@SusanthaWijesinghe-xp8rw]

buf_full signal should be asserted when the fifo_counter is 63, not 64 because it counts from 0. Therefore the statement should be corrected as "buf_full = (fifo_counter == 63);"

[@sayantikaroy9388]

The counter is initialized as 0, so it is counting from 1, so it is correct.

[@suryas7262]

No bro it has to be corrected to 63 , there initialized as 0 but after coming to 0 only it starts the count so it needs to get corrected

[@noniusreccaredus]

In the Verilog code the pointers are declared as: reg [3:0] rd_ptr, wr_ptr; shouldn't they be declared as: reg [5:0] rd_ptr, wr_ptr; So when they reach 63, then they are automatically set to zero when incremented again?

[@abhishekshankar1136]

its actually reg [5:0] cos 64 mem locations

[@korimillalaxmi7628]

@@abhishekshankar1136sir can you plz give the test bench for above fifo code

[@LucyLiu-qm1uw]

Clear explaination. Pretty helpful. Thank you very much. :)

[@unnatishah5457]

Can you share a tutorial on asynchronous FIFO counter?

[@prakharkumar1128]

Well explained.

[@bktripathi6528]

in first always block,in senstivity list only input will define .how u define output in sensitivuty list??

[@ArpitDhamija]

can you pls share source code with testbench

[@vechamvidya4499]

Nice explanation

[@ChiragHadiyaCreations]

Nice explaination b

[@DooPardoo]

excellent video

[@jayashreemm2491]

sir can u share the code for different read and write clocks

[@vishalgowtham896]

sir can u share the code

[@korimillalaxmi7628]

Is this Hdl code Or VLSL

[@rashmits1834]

Please add video for and code for asynchronous FIFO

[@ayushuniyal7035]

his lecture are in udemy

[@vanshika6384]

What is the benefit of using circular buffer ??

[@noniusreccaredus]

You mean instead of using a shift register, for instance?