What is Asynchronous FIFO? || Asynchronous FIFO DESIGN (Clock Domain crossing) Explained in detail.

Asynchronous FIFO design , explained ,if you have any doubts , please comment below ,I WILL RESPOND WITHIN 24 HR FOR SURE .
Thanks for watching ,PLEASE DO SUBSCRIBE, it will help me a lot.

[@vinad5919]

correct fifo code module afifo(wclk, wrstn, wren, wdata, wfull,rclk, rrstn, rden, rdata, rempty); parameter dsize = 8, asize = 4; localparam dw = dsize, aw = asize; input wire wclk, wrstn, wren; input wire [dw-1:0] wdata; output reg wfull; input wire rclk, rrstn, rden; output wire [dw-1:0] rdata; output reg rempty; wire [aw-1:0] waddrmem, raddrmem; wire wfull_next, rempty_next; reg [aw:0] wgray, wbin, wq2_rgray, wq1_rgray,rgray, rbin, rq2_wgray, rq1_wgray; wire [aw:0] wgraynext, wbinnext; wire [aw:0] rgraynext, rbinnext; reg [dw-1:0] mem [0:((1

[@user-qj4ku8ov1k]

What is wq2_rgray, wq1_rgray,rq2_wgray, rq1_wgray?

[@KarthikVippala]

Binary to gray conversion signals

[@user-qj4ku8ov1k]

@@KarthikVippala Thank you, I understand that. But what do these prefixes wq1, rq1 and wq2,rq2 mean? Why are there two of them?

[@CallistoPili]

@@user-qj4ku8ov1k read and write req for each clock domain

[@faisalsaeedawan5362]

I tested this code but some some data is corrupting

[@luzengyuan5326]

very detailed information about async fifo, good job

[@palmenros]

Best video and best explanation on asynchronous FIFOs, keep up the good work man!

[@KarthikVippala]

Namaste 🙏 Pedro palacios , thanks for your support and help inspiring words , good luck & great health 👍😊

[@kunliu5004]

Your explanation is very clear and easy to understand. Thank you so much!

[@KarthikVippala]

Thank you so much Kun liu ,Good luck , Good Health :)

[@shreyajoshi2453]

Nicely explained @Karthik. Kudos!

[@KarthikVippala]

Thank you, good luck, good health 👍😊

[@kkxkazuhiddles2481]

Thank you man:) That explains way more clearly than what my teacher said in class omg

[@KarthikVippala]

Your welcome 🙏

[@krishnamanohar2219]

Thank so much for clear explanation

[@raghaver5964]

Very effective teaching

[@abhinavsonkar2936]

The way of explanation is very good. It helped me a lot. Thank you so much for this video.

[@KarthikVippala]

Thanks for feedback 👍

[@bigdawg1986]

Thank you for your hard work ! Liked and subscribed!

[@KarthikVippala]

Namaste 🙏 Big Dawg , thanks for the support, good luck & great health 👍😊

[@anubisbis1846]

You are outstanding teacher. Thanks keep up the good work.

[@KarthikVippala]

Thank you so much 🙏

[@sowmyahiremath8969]

Great explanation, easy to understand.. Thank you Karthik..

[@KarthikVippala]

Namaste 🙏 Sowmya , thank for the support, good luck and great health 👍😊

[@shilpasawant634]

Very nicely explained. One comment about the FIFO depth issue. In addition to using the formula you showed, there is another way to use pointer for any non power of 2 depth FIFOs as long as they are EVEN numbers. We need to modify our pointer generation logic to pick correct rd & wr pointers. So, say we want to design a 6 deep FIFO. List all the pointer values that you would need for next power of 2 depth FIFO which is FIFO depth 8 in this case. So, for FIFO depth 8, we need pointers as 000, 001, 011, 010, 110, 111, 101, 100. We need only 6 of these values for 6 deep FIFO. So remove middle 2 values, 010 110. So now we have 000, 001, 011, 111, 101, 100 . This is still gray coded. If rd and wr ptr generation logic can be designed to generate this sequence, the circuit will work correctly. This approach will work for any even numbered depth.

[@KarthikVippala]

Hey Shilpa you are correct , I have seen this patent . Thanks for explaining it in detail, appreciate your efforts , good luck 👍

[@hankhsu1996]

Thank you so much! I've tried to find a tutorial for async FIFO for such a time, but no one can explain it so clearly like you. Hope you can make a video about how to implement this using HDL.

[@KarthikVippala]

Your welcome 👍

[@arjunnatukula7128]

good explaination can u explain how to implement in hdl

[@vinitmahajan8893]

very nice information at a depth of topic

[@KarthikVippala]

Namaste 🙏 vinit Thanks for the support,good luck & great health 👍😊

[@nimniorel]

Great video! you explained everything clearly!

[@KarthikVippala]

Thank you 🙏

[@umeshnagar4092]

Very Well explained !!!

[@arijitbomber]

Thanks for the wonderful explanation.

[@KarthikVippala]

Namaskaram Arijit🙏, thanks for the support, good luck & great health 👍😊, do you have any topics suggestions

[@sudeepbanerjee6934]

you did excellent job bro, and really appreciate your work...

[@KarthikVippala]

Thank you so much Sudeep , for such kind words, good luck, good health 👍

[@yutinggan1679]

Great video! You remind me of my favorite teacher in the college.

[@KarthikVippala]

Thank you so much Yuting Gan 👍😁. Good luck and good health brother 👊

[@mohanarajendran4332]

U r good soul 🎉🎉 excellent teaching

[@KarthikVippala]

Namaskaram Mohana Rajendran , Thanks for the support , good luck & great health :)

[@swarnikashruti5308]

Thanks for this wonderful lecture😃

[@KarthikVippala]

Your welcome, good luck, good health 👍😊

[@avinashsaini6798]

Best ❤

[@manlupiano1431]

Excellent explanation. Thanks

[@KarthikVippala]

Namaste Manlu Piano 🙏 , thanks for the support, good luck & great health 👍😊

[@namtian7]

Thank you so much. Your explanation was fantastic. Thanks again.

[@KarthikVippala]

Your welcome 🙏

[@KarthikVippala]

Hey need video on any other topic , if I know that topic , I can do a video . Recommend some topics for video please 👍

[@talupurineelima6755]

Great explanation 👏

[@KarthikVippala]

Namaskaram neelima 🙏 , thanks for the support, good luck & great health 👍😊

[@Nitishkumar1516713]

Excellent video

[@KarthikVippala]

Namaskaram Nitish Kumar 🙏 , thanks for support, good luck & great health 👍😊

[@preetamdewangansirclasses2502]

great one

[@KarthikVippala]

Thanks🙏

[@yeobig]

Super ! Thanks for explaining

[@KarthikVippala]

Namaste yeobi , thanks for the support, good luck and great health 👍😊

[@puli87]

Great buddy.

[@KarthikVippala]

Namaskaram 🙏 Bharathwaj , thank you , good luck, great health 👍😊

[@massine8214]

Thank You very much for such great explanation :)

[@KarthikVippala]

Namaskaram _/|\_ Massine , Thanks for the support , good luck & great health,Take care :)

[@sainandini2154]

Well explained...

[@KarthikVippala]

Thank you🙏

[@jagannathans2292]

Nice video👌...kindly add the links in description for other videos like binary to grey code conversion, mentioned in this tutorial

[@KarthikVippala]

Namaskaram 🙏 Jagannathan , please check out my channel playlists 👍😊

[@wndell3722]

So Clear ！！！！！！！！ omg!! Thank you, sir!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!1

[@KarthikVippala]

Thank you so much 👍

[@saitejareddyg3034]

very nice explaination

[@KarthikVippala]

Namaste Sai teja reddy, Thank you so much , Good luck & Great Health :)

[@prashanthra6031]

Very good explanation

[@KarthikVippala]

Thanks and welcome

[@beautifulcrafts8548]

Superb awesome explanation....

[@KarthikVippala]

Namaste 🙏 beautiful crafts , thanks for the support, good luck & great health 👍😊

[@beautifulcrafts8548]

Please do the videos on RTL integration

[@amruthats8648]

Thankyou so much!! you are a very good teacher. all the best yaar...

[@KarthikVippala]

Your welcome, good luck, good health 👍😊

[@cheesepie4ever]

Great video thanks! Subbed

[@KarthikVippala]

Your welcome

[@mayurpatel9349]

This is very helpful

[@KarthikVippala]

Thank you!

[@roni5884]

Nice video

[@KarthikVippala]

Thank you 🙏

[@CallistoPili]

very good video, there is still one missing point there, the timing contraints for a async FIFO. :)

[@zenithchokshi9365]

Hello Karthik, Thank you for the amazing explanation. I got all the points but I have one confusion in metastability, I mean you are supposing a "1" for FF 1 op that works as an input for 2nd FF. What if you take the FF1 output as 0? Can you please explain this condition? Thank you!

[@shivu4377]

Very nice video.. Can you please explain us how a metastable signal recovers during synchronization.

[@raviteja1367]

Can you please explain Amba-apb and Amba-ahb protocols in detail?

[@bhavyachowdary3526]

Hi Karthik It's an amazing explanation. Could you please let us know what are the changes need to be made to the design code pinned when Dual port asynchronous fifo has 2 write ports and 1 read port. All the three ports are working on different frequencies. The inputs ports have the capability to write simultaneously based on Write enable signal. If both ports try to write then port1 will be given the priority. Thank you.

[@amirraeisi1366]

Excellent and thank you. If you can control the excitement in your voice it will be much better. Thank you for the explanation.

[@KarthikVippala]

Improving on it 🙏

[@yashvirchauhan385]

Hi Karthik, I work in VLSI company and needed to develop FIFO IP Core. ur lecture had a great explanation and covered all basics ,keep up this good work .Also, Plz could u provide material of this lecture somehow. Thanks

[@KarthikVippala]

Hey yashvir, for the reference you can check asynchronous FIFO papers in Google scholar. Be patient while reading the papers , if you have any doubts , please feel free to comment 👍

[@yashvirchauhan385]

@@KarthikVippala Can u make videos on AMBA protocols..that will be very useful.Thanks

[@KarthikVippala]

Hey yashvir , thanks for asking , I will try to make , but Amba is huge ,it will be better if you read the specification and ask the specific topic . I will help you with doubts 👍

[@kavyatamatam6245]

@@KarthikVippala can u please make video on writing functionsl coverage for a moduke

[@onkardesai30]

Dude, you need not say subscribe so many times.. Most of us subscribe half way through the video looking at the way you explain..it's very good!

[@KarthikVippala]

Namaskaram Onkar Desai🙏, when I made that video I had 150 people watching , so I was desperate 🙂, I have improved , thanks for supportive words , good luck & great health 👍😊

[@onkardesai30]

Namaskar @@KarthikVippala 🙏 Looking forward for more content!! Good luck and good health!

[@minqingliang6211]

Thank you so much for making such great videos!!! Could you make some videos about JTAG, APB and iJTAG for DFT?

[@KarthikVippala]

Sure🙏

[@minqingliang6211]

@@KarthikVippala thank you, can’t wait for it!

[@shilpa4600]

Greatly explained Karthik. Got a chance to come across ur videos, and it is helping me a lot in understanding the concepts at base level. Cleared many doubts and very neat explanation. Learnt many things from the doubts raised by commenters also and your explanation of those... Could you please share VHDL code for FIFO design which you explained above. Would be more helpful in understanding it in implementation level. Please let me know the media for sharing RTL for this, would like to connect for further doubts. Thanks A lot. Keep rocking.. Be healthy.

[@KarthikVippala]

shilpa , that's longer than my video 😊 , thanks for the supportive words , you can ask any doubts here even regarding code . Good luck, good health 👍

[@aishwaryanair7047]

Thanks. That was a very clear explanataion.

[@KarthikVippala]

Your welcome 👍

[@KarthikVippala]

Do you have any suggestions of topics for the channel 👍

[@aishwaryanair7047]

You can add videos on Low power design techniques.

[@KarthikVippala]

@@aishwaryanair7047 thanks for your suggestion , I will try to do videos on them.

[@balasubrahmanyamp6406]

thankyou sooooo much

[@akshay5041]

Great Video . Could you explain a bit more on why gray code is needed .

[@KarthikVippala]

Namaskaram Akshay🙏, gray code is used to perform proper synchronisation , in normal binary we will get false full and metastability. Good luck, great health 👍😊

[@pratikkaul77]

How are you not famous damnnnn

[@KarthikVippala]

Thanks 😂, good luck & great health 👍😊

[@1amswill]

Great explanation man! Is your in-depth understanding due to reading and research or work experience?

[@KarthikVippala]

Thanks 😊. Good luck 👍

[@vatsala900]

thank you ...

[@KarthikVippala]

Your welcome 👍😊

[@ranjanparnami]

Thank-you...

[@KarthikVippala]

Namaste 🙏 Ranjan Parnami, thanks for the support, good luck & great health 👍😊

[@adityasarda74]

In case of non power of 2 fifo depth how would we detect the wrap around condition? Appending an extra bit to msb and detecting the overflow would only work in case of power of 2 right?

[@annankldun4040]

Great video but the explanation to when we know the difference of full and empty (16:00) is confusing. If we flip the MSB of waddr and then the values of waddr[3:0] are the same as raddr then its full but that can also hold for the case when wadder is empty i.e.: wadder with 5 bits is 00000. Negate MSB: 10000 == raddr at empty. I'd appreciate a clarification here.

[@kanthimathis6556]

Hi Karthik, thank you for making very informative videos. Please, clarify this doubt of mine: positiveskew helps meet setup time. But, slow corner ( min voltage, Max temperature_more delay) is the worst for setup. Can you tell me why slow corner is bad for setup, please?

[@arjunmenonkandanat6328]

thankyou so much

[@KarthikVippala]

Your welcome, good luck, good health 👍

[@rengapradeep]

thanks

[@KarthikVippala]

Namaskaram _/|\_ Renga Pradeep, Thanks for the support , good luck & great health, Take care :)

[@dheerajha6638]

Please make a video on C2MOS about how its insensitive to clock skew

[@shyamabz4414]

Hey Karthik, Thank you so much for you video. Can you please upload an video on following design questions:- 1. Design of Synchronous Circuit to detect the toggling of flip flop. 2. Edge detector Circuit i.e to detect whether the Flip flop is +ve edge triggered or -ve. Thanks in Advance for your response

[@KarthikVippala]

Hey abarajithan, I Will make it but need some time . Thanks for asking 👍

[@shyamabz4414]

@@KarthikVippala Thanks you so much your, the best ! if you could explain about round robin arbiter design that would be of great help! Appreciate your efforts and your time !! thanks a lot

[@KarthikVippala]

Hey abarajithan , I will do them, but I will ask some questions while making the video. To know what exactly you need 👍.

[@KarthikVippala]

Hey abarajithan , edge detection means edge detection of input or not. Can you please elaborate about toggling of flop

[@NUNUA]

Can you please advise for syncing from one clk to same clk freq but with different phase, what would be the minimum depth? 2? 4?

[@krishnamanohar2219]

Thank you so much for clear explanation

[@KarthikVippala]

Thank you for your feedback and support. Can you suggest any other topic , that you need .If I know it , I will make a video on it. Please do subscribe it will help me a lot.

[@krishnamanohar2219]

Division algorithm by any number. i was bit confused, can you please help me on this Thank you

[@KarthikVippala]

@@krishnamanohar2219 can you be more specific , what is division algorithm?

[@KarthikVippala]

Do you mean clock divided circuit?

[@krishnamanohar2219]

for example 12/3 = 4. i want this algorithm how to implement in digital design

[@PEC_SIBASISHMOHANTY]

Sir Please make a video for synchronous FIFO

[@kavitamishra8928]

Hi karthik..if the wr_req is too fast then wr_cntr increment may be lost..i mean u said for grey cntr, either value will remain same or it will be synchronized..but by the time synchronizer settled what if the grey_cntr has already incremented by twice and u miss one value in between?

[@kankanasarkar7439]

Thanks for the video. I have question regarding the depth of asynchronous FIFO formula that you mentioned at last. This formula is taking FIFO Depth . So this range is specifying what exactly?

[@KarthikVippala]

Namaskaram 🙏 kankana , formula is for calculating range in case of non power of 2 depth , you can check fifo depth video on my channel for better understanding, Thanks for asking 😊, good luck & great health 👍.

[@nagakeerthanakanagaraj2195]

great explanation! Can we get same kinda explanation for FIFO depth calculation

[@KarthikVippala]

Thank you for asking, please check video of Fifo depth consideration , link below kzbin.info/www/bejne/eoLYn3eqeZuMmNU

[@KarthikVippala]

Do you need any video on any other topic , if I know that topic I can make a video on it.

[@nagakeerthanakanagaraj2195]

@@KarthikVippala sure Karthik I ll let you know about it and thanks for spreading knowledge

[@shridharasmaryapura1504]

can you explain the internal architecture of the all the 3 major blocks such as fifi mem, fifo wr_ptr, fifo rd_ptr, synchroizers

[@KarthikVippala]

Hey shridhara , thanks for asking the question, FIFO men contain memory element ie flip-flop , registers Wr_ptr and rd_ptr contains storage elements to store the value of pointers and comparators for comparing the values and some extra logic gates. Hope this clears your doubt , if you any more I am happy to help you 👍 Please do subscribe it will help a lot . Thanks for asking

[@omersarcam3070]

When we apply this, due to 2 synchronisers, when the fifo memory is full, the full signal becomes 1 after a few cycles. Won't this cause a problem? Because the full signal occurs much later. Since the full signal is given late, data continues to be put into the fifo memory even if the fifo memory is full.

[@zvikacohen]

Thanks for the video! Why not sync rd_en and wr_en to generate empty and full condition? (no need for gray convertion)

[@anandkumar-bd2ru]

To get syn rd_en , we need to do gray convertiona and pass through 2 flop synchronizer and back to binary syn rd_en. I guess.

[@ashishdudeja9466]

Great explanation , though I miss to understand one thing. When using async FIFO we need to use one extra bit to determine full flag. This extra bit also goes through binary to grey encoding ? For example , if the FIFO depth is 8 then I have to use a 04 bit or 03 bit binary to grey encoder ? Thanks for answering.

[@KarthikVippala]

Namaskaram Ashish _/\_ , Thanks for asking , Yes extra bit also go through encoding, for depth 8 we need to use 4bit. Good Luck and Great Health , take care :)

[@ashishdudeja9466]

@@KarthikVippala Thank you .

[@saicharan3367]

At 6:45, what is the guarantee that the signal is going to be to be sampled to 1 ? after meta stable state, the signal may even sample to a 0 value right? how can we know the correct value from 2 flop synchronizer?

[@ap8185]

I thought the read pointer and write pointer point to the address in the memory to read and write from. Why is there a waddr and raddr? Why are those there? And why do they not need to be synchronized?

[@PradeepSingh-kp6tu]

hissing noise is good:))

[@PradeepSingh-kp6tu]

In your toggle syn (cdc) why pulse with is increased as you said in 2 ff syn pulse can't detect. Ap you decided to use.. Toggle syn. But in toggle syn your pulse width is changed. So what you want to say.

[@KarthikVippala]

Will get bck need to look video once

[@PradeepSingh-kp6tu]

@@KarthikVippala will wait

[@satheesh3210]

Please can you explain in detail about flop synchronizers in detail

[@KarthikVippala]

Namaste 🙏 Sathish , pls check my channel playlist :synchronizers where I explained about it in detail, good luck & great health 👍😊

[@Migellitos]

Dear Karthik. Could you explain does it matter for synchronization whether Fifo_mem is pure registers reg mem[DEPTH-1][WIDTH-1] or true dual port RAM? In other words if I use just simple registers as a fifo memory does synchronization still works?

[@KarthikVippala]

Hey Migellitos , thanks for asking the question , Synchronization will work in either case. Reg mem will work fine , for Synthesis it's better to use memory model. Good luck, good health 👍

[@inamulla8156]

Hi Karthik , Greatly Appreciate your work and efforts for this wonderful explanation, I have a dbout in Depth calculation part. How did you consider as (2^10)/2 for that 520 depth FIFO calculation, Is it a approximation OR How?. please do the needful Thankyou.😊

[@RahulKumar-oz2mc]

@karthik, same doubt. What is 'n' here?

[@mvrajesh1]

the latency between write_pointer and the comparison on the other side is many clock cycles, how will this system work ?

[@tinhlac1405]

Ihave little confusion on the empty and full condition. Because the synchronizer, the wrptr and rdptrt will be value of previous 2 clock cycles. When you use that to compare how does it work. Ie let say you want to compare empty condition. You would compare it in rd_clk domain. However, the rdptr value of rdptr is the current address of this clk cycle, but the wrptr is the old value of wrptr of previous 2clk cycle. Because of that, it does not compare to the current value, the empty condition is not a really empty.

[@KarthikVippala]

Hey Tinh Lac, I understand your confusion , yes when the rdptr is passed to the wr_clk, there could be 3 to 4 clock cycles delay , with respect to rdptr in rd_clk domain and rptr value in wr_clk domain may reflect older value. This means more space is available in FIFO to write than what it is showing . When reading is stopped rdptr will catch up to the value of real rdptr. This will not effect the performance . Similarly when wrptr is passed to rd_clk domain , wrptr is 3 to 4 cycles delay compared to real time wrptr. If empty flag is generated , since we are writing there could be few data in FIFO ,when writing is completed this wrptr will catch up to the real time wrptr. There is a temporary lag in pointer value , which gets updated to correct value in several cycles. Hope this clears your confusion , if you any more doubts feel free to comment. Please do subscribe it will help me a lot 🙏

[@tinhlac1405]

Karthik Vippala just sub

[@KarthikVippala]

@@tinhlac1405Thank you 🙏 so much

[@kalyanipolipalli]

Hi Karthik, Nice explanation. This formula applicable for FIFO depth is Even. What will be the procedure for ODD FIFO depth?

[@prasanth669]

just round up to next even number, thats the simplest way

[@AmitKumar-wf1qq]

thanks for video, sir i have one doubt that if we use 2 flip-flop synchronizer then it will delay one read_clk for generating empty condition check and similarly one write_clk for for generating full condition. so due to this delay we may read from empty fifo or write to full fifo. therefore what should i do to avoid this delay and generate full and empty condition in real time without any delay?.

[@ChrisSmith-tc4df]

The 2 clock delay makes the full and empty conditions pessimistic as the two points approach each other. Ingress will read full a bit earlier as information about a very recent withdrawal is delayed. Egress will read empty a bit earlier as information about a very recent deposit is delayed. If the two sides have similar throughout, a performance issue can arise as it buffets around both empty or full. This approach works best when the ingress and egress rates are sufficiently different to accommodate the delay in information between the two sides.

[@gayatri5397]

when converting 101 to 110, can all the bits of 101 change to 000? or how does metastability work?

[@garimagoyal6604]

What if output of QB1 settles to zero after metastability state? Then we are getting the complement of QA as the final output and eventually the use of synchroniser complemented the output

[@garimagoyal6604]

I am asking from where you told about the two flop synchronisers

[@placementdas3997]

Even after grey code conversion we are not getting our desired result. As you said for grey 111 -> 101 we will be getiing 111 or 101. But they are two different counts , one indicated the number of data in the fifo as 5d other as 6d. Wont we have an error in the result ?

[@hgl9590]

I have the same question!

[@nabeelahmad4583]

great work bro..

[@KarthikVippala]

Thank you brother, good luck, good health 👍

[@nabeelahmad4583]

@@KarthikVippala hello bro can you tell Circuit for 1st one finder for a series input

[@KarthikVippala]

@@nabeelahmad4583 hi , I did not get you ,can you please elaborate 👍

[@nabeelahmad4583]

@@KarthikVippala there is series of number entering in logic circuit,when 1st 1 enter output should be high

[@KarthikVippala]

@@nabeelahmad4583 are numbers binary

[@vagallamallikarjunareddy6177]

hi Karthik please provide information on CDC, LINT and SYNTHESIS

[@KarthikVippala]

Namaskaram 🙏 mallikarjun, please watch cdc playlist on my channel, lint synth will update but it will take time

[@vagallamallikarjunareddy6177]

Thank you karthik

[@syedahmed1360]

Because of using the synchronizer, the pointer value in one domain are compared with the delayed pointer value from other domain? Will that not be an issue

[@KarthikVippala]

Hey Syed ,thanks for asking the question, Let say, when read pointer is passed to write clock domain, there can few clock cycles delay(2,3 or 4) with respect to rd_ptr in read clock domain, and this may reflect older value in rdptr_wrclk, this means there is more space in FIFO but its not reflecting due to delay of synchronizers , this will not effect performance or will not cause overrun. When reading is stopped rdptr_wrclk will catch up with rd_ptr in few cycles delay and this happens similarly write pointer. when write pointer is passed to rd_clk domain there can be few clock delay. An empty flag will be generated even when we few data in FIFO this completely fine this will prevent from Complete empty (it indicates almost empty :)....) and eventually when writing is stopped wrptr in rd clk domain will catch up. Hope this clears your doubt , please do subscribe, it will help me alot , and please suggest some topics for upcoming videos. Good Luck, Good Health :)

[@sonnguyen3874]

Hi Karthik, does your professional regard to Verification also? If yes, I'd love to see some verification techniques from you.

[@KarthikVippala]

I will do videos on it in future 👍

[@sushmakakarla7657]

Can a fifo take packets of data from one port and deliver it to 3 different destination based on destination id at same time. To bd simple can a asynchronous fifo have 3 output data ports

[@KarthikVippala]

Namaskaram Sushma Kakarla , Yes you can connect output to multiple ports , Thanks for asking, Good luck & Great Health _/\_ , Take care:)

[@ADITYA95KUMAR]

Hey Karthik, Great Explanation!! I have a question regarding the synchonization of Gray Counter. Suppose there was metastability during the CDC of gray counter, beacuse of this the value sampled in receiving domain is same as the previous value(intended value was incremented value). How do we take care of this situation as the pointer was supposed to increase but it didn't? Wouldn't it cause the false empty/full condition? Does the pessimism introduced in the design take care of the above condition as well?

[@KarthikVippala]

Hey Aditya , thanks for asking ,if it some how system enters metastability , pointers will not be changed, even if pointers are increased we will send the same values again so pointer will not be effected . Good luck, good health 👍😊

[@ADITYA95KUMAR]

@@KarthikVippala One follow-up question, let's consider the corner case..if the pointer would have incremented it would have caused empty/full condition but, due to metastability as you pointed out the pointer will not increase and the same value will be sent. Now the comparison module will compare the read and write pointer value and since the value doesn't satisfy the empty/full criteria (although it should but it didn't due to metastability) so, the enable single will remain asserted and read/write will happen. Since we are taking about the corner case, this would mean that we are trying to write to a full FIFO or read from an empty FIFO, thus violating the criteria of FIFO design. Am I missing something here? Thanks again for your time.

[@KarthikVippala]

Why will enable signal will be high ?

[@ADITYA95KUMAR]

@@KarthikVippala Because one of the inputs to the and gate of enable logic is driven by empty/full condition. Since we didn't see the full/empty condition, the enable remained asserted.

[@KarthikVippala]

@@ADITYA95KUMAR full and empty condition are dependent on wraddr and rdaddr , so I guess it won't be a problem . Can you please make question short , I am unable to concentrate for whole time😋.

[@kavinduvindikasomadasa352]

but you haven't mentioned what happens with wr_data and rd_data....how can we store them inside the FIFO MEM if we are using 2 clk domains. As you mentioned gray codes are possible for multi bit transmission (but it's used for 1 bit changes...in actual data, it can be random)

[@JaganJohn]

FIFO is filled only with 1 clock say wclk. wr_data will be synchronous to wclk. rd_data has nothing to do with FIFO writes.

[@sonnguyen3874]

valuable video. Just subscribed to your channel. No offense, could you tune your voice that will help people feel more comfortable.

[@KarthikVippala]

Thank you son nguyen , I will improve on my voice , good luck, good health 👍

[@sonnguyen3874]

@@KarthikVippala hi Karthik, I have 1 concern: Will 2-FF syncer work correctly if write_clk is much faster than read_clk or vice versa? Any data lost?

[@KarthikVippala]

@@sonnguyen3874 no data won't be lost , we need to take care of overflow and under read .we might get some clock cycles delay but that's fine

[@SaiAnirudh_warmacheene]

at 5:54 you said Flob B is in a Metastable state due to setup time violation. But then the output could settle to either 0 or 1 right? what if the output settles to 0 when input is 1? Isn't this causing a bit of error? How do we solve the bit error and ensure correct data transmission without any errors in bits? because 2FF synchronizer doesn't guarantee correct data transmission it only guarantees clean data transmission right?

[@ChrisSmith-tc4df]

This metastable bit confusion is exactly why Gray Code must be used between the clock domains, so that only one bit changes at a time as the pointers increment. The worst case is that the transmission of the pointer remains at the old value a clock longer before advancing to the next possible count.

[@vikineo]

In that formula, how do you come up with the value for "n"? is it "the first power of 2 number" after the given fifo depth?

[@KarthikVippala]

n should be such that it is greater than depth, let say depth is 520 , n will 10 as 2^10 is 1024, If depth is 9,n will 4 , 2^4 is 16. Thanks for asking, good luck.

[@Anil-yo3tx]

Thanks for the video! Question: For 520 depth you got 252 and 771 as addresses. But once FIFO is full we cannot roll over to 252 since we cannot decipher between empty and full. Instead do you think equation should be 2n-depth to 2n+depth-1 to cover for empty/full case and also Gray code rollover?

[@KarthikVippala]

Namaskaram 🙏 anil , thanks for asking, when we use 252 and 771 address , when fifo is full we rollover to 252 not zero.

[@Anil-yo3tx]

@@KarthikVippala Yes I understand it doesn’t go to zero. If FIFO is full it goes to 252. If FIFO is empty it also is at 252. Then how do you decipher between full and empty?

[@JaganJohn]

@@Anil-yo3tx You need an extra bit in address for detecting rollover

[@unnatishah5457]

@@JaganJohn In that case , while rolling over that extra bit will change from '0' to '1' and also MSB will change from '0' to '1' since we are rolling over from address 771 to 252. So now we have two bits change in gray code while we roll over. Can you explain that?

[@unnatishah5457]

@@KarthikVippala Aren't we considering extra bit for roll over to decide FIFO Full and Empty condition? If yes, then there are change in two bits while rolling over. 1. MSB changing from '0' to '1'. 2. One bit change while switching from 771 to 252. Can you please explain how this would work?

[@ExploreElectronics]

Thanks for the video. I have a doubt here. please clarify. if we consider extra bit for address/pointers, full and empty can be set correctly. what happen to the next address of FIFO, i.e, 1000? how to roll off? if rd pointer is not 0, will it not try to write on 1001 location and so on? PLEASE ANSWER

[@ChrisSmith-tc4df]

The extra bit is only used for comparison, but masked off, so that only the lower bits are used as the memory address.

[@KarthikVippala]

Thanks Chris 🤝

[@ExploreElectronics]

@@ChrisSmith-tc4df thankyou