CMOS inverter power simulation | low power design | sky130 | Xschem | EP7:VLSI Project help

[@vishwajithvpai5781]

Rajdeep Sir Very useful series that covers all the basic concepts , helped me in revising most of the concepts along with getting practical experience doing the project, cant wait for the the layout video, All do like the video for better reach and to support Rajdeep Sir.

[@kapilsingla1228]

It's really helpful. Thanks a lot rajdeep and waiting for your next layout video.

[@ritikasharma-tf6kd]

how can we design cmos subthreshold inverter ?

[@parthikirubha]

One doubt ! Please Clarify , What is the full form of Vdd,Vcc, Vss.....What does that mean ?

[@rohitpathak7088]

Bro please google it...this is basic qtn

[@whyRD]

They are just the power source , vdd coming as its connected to drain and ground , if its a voltage connected to drain and source we would have called it vds , and vcc coming from bjt terminal… and vss again its connected to source …. Basic but a interesting question

[@divyatiwari8436]

hello sir!! will you upload the layout part for this project if not please guide a little regarding the same. also thankyou for this series.

[@whyRD]

Will release today only , sorry for such a long wait 🙃

[@electro.feedback]

Hey is it possible to generate netlist just by verilog coding, can you start this after 30 days verilog series is over

[@whyRD]

Yes from verilog you can directly synthesise it to netlist

[@krishnadhas2232]

Is there any possible to learn magCAD tool for pnml?

[@animestalker7485]

Brother suggest me some free tools for basic learning of vlsi pls I am in 4th year and i wanted to try making a vlsi based project

[@DiganthaH.D]

Brother in vlsi engineering physics will be there i just paaed out 12what i have to study to get 9cgp in vlsi engineering

[@DiganthaH.D]

Sorry it's passed12th

[@electro.feedback]

awesome

[@jmraii8847]

*Promo sm*