CMOS NAND Gate

[@TutorialsPoint_]

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[@shivamsoliya6529]

You've explained every logic circuits perfectly. Heartily grateful to you ma'am.

[@subarnamondal3787]

the way u discussed was very nice...understood the entire thing clearly...keep making videos...

[@matthewghere7765]

This channel is goated. You are the reason I am passing my EE classes in undergrad

[@uzmasakhiullah3792]

Oooo thank you so much dear mam❤❤i have seeing this before two days of exams ....n i got it 😍😍❤❤once again thank u❤

[@shahistaa8723]

ur a great teacher each students dream to have..just by one explanation urs we will understand everything.. 🙏🙏🙏..great guru ur..

[@mdmonazirkhalifa3997]

Thank you ma'am for the simple and good way explanation

[@Car-infotech8055]

maam you teach me in very easy way . i watch many video but i understood only through your lecture .

[@prohightension2000]

Thank you for making this so easy to understand!! You saved a lot of my time :)

[@harichandanaveerandi1963]

Sister u explanation is gud but if u provide captions it is helpful fr us fr writing notes hope u consider it

[@bonerici]

I had no problem understanding her to be honest

[@jayantmishraES]

Muchas Gracias mi maestra para ayudándome . Que significa mucho para mí

[@kqapex4852]

Our sir sent us back to learn this and come for viva or else he will roast us..after watching your video we got 10/10!!! Superb ma'am ❤️😀😀😀

[@ngarambefrancois5319]

You answering my questions well, thanks

[@anime_thrones_endgame]

how i get this full play list..????🙄🙄🙄

[@saicharan3367]

Mam,in c mos nandgate,what is the use of connecting two n mosfets rather than connecting it directly to the ground as that of p mos nandgate.i mean that the use of those two nmosfets has no effect.i.e the output is dependent on pmosfets.

[@shivanisorte7088]

brilliant video ma'am. thank you so much

[@circuitsanalytica4348]

Yes, really nice video, isn't it?

[@dinijatt5615]

Easy to understand explanation

[@bunkey_085]

thanks for this wonderfull explanation

[@vijayvaghela4632]

Very nice explanation mam.. Great 👍👌👍👌👍👌👍👌👍👌

[@wolfzzf]

Very nice tutorial

[@vijayalakshmi9591]

Will u teach NA(network analysis)..

[@mahmoudalien]

Amazing Video, Thank you

[@n.p.9997]

Great explaination. Thank you mam.

[@pmbolivia5085]

best explication ever....thank u !

[@circuitsanalytica4348]

Yes, really nice video....

[@aryandhakad8495]

This video u not put it in playlists,sis

[@eddytech2229]

Nice presentation Clearly explanation Thank u ❤️❤️

[@circuitsanalytica4348]

Yes really nice video and nice explanation

[@mdmonazirkhalifa3997]

Ma'am please make a video on 3 inputs NAND AND NOR GATES BY CMOS

[@vanikoduru403]

Very good explanation

[@champ4753]

thank you madam😇blessings be on u

[@vikramsimha70]

Thanks for your class mam

[@danielamare2685]

woow beauty lady your tutor is very nice!! Thank you very much!

[@circuitsanalytica4348]

Really nice video, isn't it?

[@circuitsanalytica4348]

Nice video....

[@JASPREETSINGH-dx9ju]

mam you explain very perfect

[@circuitsanalytica4348]

Yes really nice explanation....

[@Jatin.Mudgil07]

Thank you mam

[@saiabhinpatil2958]

Nice explanation madam

[@manishshrestha2539]

Yet we are where we begin... What's piety and impiety?

[@yeswantyadav3277]

Excellent Explination mam

[@venkatanaveenmorla7513]

Nice explanation Mam thank u very much

[@hamzachaudhary2755]

if we will invert positions of NMOS & PMOS so it will become AND gate? Please help, thanks

[@Joyful470]

I also notice this..

[@circuitsanalytica4348]

No, if you use an inverter at the output it will work as an and gate.

[@jyothiss7066]

is the connection to ground is necessary for a 0 o/p? ie, if the o/p is neither connected to Vdd nor ground, will it give a 0 o/p?

[@circuitsanalytica4348]

No, output will be at high impedance state. In this case output is either 0 or 1

[@rahulrajalingam8432]

Mam your teach is very good & I have one dout did you explain the ECL in next video

[@circuitsanalytica4348]

Shall I make video on ECL?

[@sanjayss5584]

Your really great mam and thanks mam

[@vanikoduru403]

Easily understandable.....

[@increderereddy-md5vv]

Can you Draw a NAND gate using only 3 transistors?

[@valliyappans9949]

good and clear explanation.. Thank you mam

[@circuitsanalytica4348]

Yes really nice videos

[@remandey4368]

Thank u so much...

[@Naveenkumar-he9jk]

Your explanation good madam

[@vanshverma2647]

OP EXPLANATION👌👌👍

[@akashjaiswal2693]

Ty madam for explanation

[@GILAD555]

Great explanation!

[@vidhyabhodana954]

The way you explained is good but why cant you draw the circuit while explaining rather drawing it at first

[@MATHEMATICSBYNITianHimanshu]

thanks mam

[@wil00000]

ótima explicação, obrigado!

[@circuitsanalytica4348]

Can you please repeat in English.....

[@Shree29k]

Nice

[@raghuvulli]

thank u very very much mam

[@kashan-hussain3948]

Thank you Ms

[@vikrantnegi6190]

Mam what is CMOS two four input NAND gate

[@nazmul817]

MANY MANY THANKS

[@saimanojmanoj8966]

teams.microsoft.com/l/message/19:[e-mail]2/1598413137848?groupId=112929d5-7a03-4aab-897b-8cbc9e4e254f

[@hiteshchavda5505]

Powerful lady..

[@Lynxsis]

thanks mate

[@N_santosh]

How u drawn the diagram mam

[@kkrvideos7539]

TQ mam 👍

[@mahithareddy7874]

can u share and gate and or gate by using cmos

[@circuitsanalytica4348]

I will make a video on and and or gate. Shall I. ? It is very easy, connect a not gate at the output of NAND and nor gate?

[@notrahul9572]

Op explanation🔥

[@reetupoudel4141]

Thank u😊

[@hiteshchavda5505]

Beautiful..

[@umamaheswari-cr1bp]

2 input nand gate using cmos Ela construct chestaroo cheppandi

[@circuitsanalytica4348]

Can you repeat in english?

[@vyankateshdhage8315]

thanks you

[@chevurubindu1357]

Tq madam 😘

[@chandramoulisharma3312]

how can I draw this structure with the help of nand truth table....

[@circuitsanalytica4348]

Realise the circuit using NMOS, then take complement of that network, means if NMOS is a shunt network, PMOS becomes series network and vice versa

[@circuitsanalytica4348]

For a NAND gate, output is 0 if both inputs are high, that means pulldown network should conduct when both inputs are 1.This happens if and only if NMOS transistors are in series. If any one of the inputs is 0, output must be 1. That means PMOS should conduct if any one of the two inputs is 0. That means PMIS are in shunt - just opposite to the NMOS connection

[@veerapallirohith8449]

Super madam

[@abhigyandeori9085]

Ma'am please make a tutorial on SRAM

[@circuitsanalytica4348]

Shall I make a video on SRAM?

[@saipriyavlogs7806]

Mam naku eca link pentundi

[@sazzadulislamshovon4819]

What a explanation

[@sishirjana565]

valo hoeche

[@acem20242]

Nice ma'am

[@saikatmondal8704]

Thanks

[@saipavithra4630]

Madam can u provide notes

[@luizferreira3986]

Thank you so much

[@circuitsanalytica4348]

Nice video right....

[@anjumanju9951]

thanks maam

[@CLOKESH-xh5gg]

2-input AND&OR gate explain

[@435mahendraepparla3]

Subtiles needed mam

[@telugueswaramma3541]

Tanks mem

[@justsanaldhings4587]

🔥🔥🔥🔥❤️

[@buntyGamer101]

Mem hindi ne samja dijiye

[@sarveshsk2315]

Circute😅😅😅😅😀😀😁😁🤣😂

[@pawecegieka7790]

NOT HELPFUL

[@soundsoftheworld892]

RIP English

[@md.mokshudulmomin2861]

thanks mam

[@MuhammadShahzad-ni1ix]

Nice

[@Ray_yt666]

Thank u so much.

[@thenewstarshorts52]

Thanks so much mam

[@panditsasirekha]

Thank you mam

[@circuitsanalytica4348]

Really nice video, isn't it?

[@nikhilk31]

thanks

[@rakshithreings7701]

Thank u mam

[@Naveenkumar-he9jk]

Thank you madam

[@MANOJKUMAR-dv1gs]

Nice