CMOS Logic Gates Explained | Logic Gate Implementation using CMOS logic

[@ALLABOUTELECTRONICS]

For Notes on CMOS Logic Gates, check this article: www.allaboutelectronics.org/cmos-logic-gates-explained/ For more videos on Digital Electronics, check this playlist: bit.ly/31gBwMa

[@TechnicallyExplained]

I made video on this CMOS a year ago.. But hats off to you... I just wish I could provide explanation like you

[@jayeshlale1999]

It's still helpful out of all the resources available on this topic across youtube. 👍👍

[@codexgaming384]

The most relatable video on youtube to the point and this is perfection......................sir love you and thankssssss 🥰

[@Christina-ul8hw]

Exam in 4 hours and the professors notes were so confusing, thank you so much for this video I understand everything I needed within 15 minutes T-T

[@free_storageee]

This lecture is really helpful and much easy to understand 🤩

[@Shalini-cc3]

Thank you so much for this nice explanation ☺️

[@poojashah6183]

Definitely you are the amazing tutor 👌🏻👌🏻

[@mayurshah9131]

Absolutely superb

[@092_ditamondal8]

best and very much helpful vdo.....thanks a lot☺

[@adityarao5636]

very good explanation

[@adityamaheshwari4250]

Brilliant explaination🙏

[@रोहित1]

Thank you ❤️

[@mahakgupta455]

very helpful video,thanks

[@neophytegs4094]

Very well explained

[@shriganeshayenamah3422]

thank u very much sir

[@vaarunaramakrishnan6122]

Amazing video

[@ShenhavBiton]

amazing video thank you very much!

[@SureshSuresh-xs8bj]

Sir I have one doubt how pmos is pull up network and nmos is pulldown network

[@ALLABOUTELECTRONICS]

When PMOS is ON, it will connect the output node to VDD. So, it will pull-up the output voltage to VDD. (That's why its called pull-up network) On the other hand, when NMOS is ON, then output node will get connected to the ground via NMOS transistors. So, we can say that, the NMOS transistors are pulling down the voltage at the output node to logic'0'. (And that's why they are called pull-down network) I hope, it will clear your doubt.

[@faneeshbansal]

22:26 , sir there is one more representation of xor gate that is possible in which we have PDN network in series form only, pls make a short video on that comparing that representation with this one,

[@ALLABOUTELECTRONICS]

Yes, will try to cover that too.

[@anonymous9217w2]

@@ALLABOUTELECTRONICS sab cover kr lo jai mahakal!

[@Priyanka-vx4ym]

Thank u sir

[@harshithgoogly]

Can you please explain why your ignoring bar(‘) and writing A.B While constructing NAND gate. How the bar(‘) operation takes place here

[@ALLABOUTELECTRONICS]

Would you please mention the timestamp where you are referring to in the video ?

[@pravinthakare8140]

Sir please make playlist on ic 8051 and ic 555

[@ALLABOUTELECTRONICS]

555 is already covered in detail, please check this playlist for more information. kzbin.info/aero/PLwjK_iyK4LLCVdgBR30pSFVj-17TI_8ou

[@pravinthakare8140]

@@ALLABOUTELECTRONICS thankyou sir for this help^⁠_⁠^

[@suryas7262]

but there must be a connection between source and drain right 4:03 (you only showed voltage between gate and source),you have not showed in this video or am i wrong

[@arjunkrish30]

What happens when we connect Vdd to nmos and vss to pmos ??what will be the output

[@pramodkadam1998]

Nmos and pmos will be always on

[@winlose3073]

at 4:23 you say the output voltage when the mosfet is open is 5vs. how is that possible to be 5vs with the presence of a resistor?

[@shreyasmanak6994]

Sir arrows waale pmos cmos use krlo pleaseee

[@suryas7262]

15:14 here if arrow denoting outside means p channel and inside means n channel but you done opposite here how it is acceptable

[@ALLABOUTELECTRONICS]

It is other way around, the arrow going outside denotes n channel and arrow going inside denotes p-channel. The upper one is p-mos and lower one is n-mos transistor.

[@suryas7262]

@@ALLABOUTELECTRONICS sir thank you for your reply so that means it is your assumption right?

[@Priyanka-vx4ym]

Mosfet exists in depletion and enhancement mode, for depletion it is similar as jfet, for enhancement mode it is opposite to that

[@shubhamsingh4606]

sir can we get pdf of the complete playlist

[@s1ghtern]

its really good but pls don't speak with an Indian accent its really hard to understand ;)

[@Schuesse_in_die_Luft]

There are subtitles if you don’t understand. A person cannot change the accent from one day to another. Stupid comment

[@anonymous9217w2]

so beacuse of you only, he should change his accent, cmon he is teaching for free on youtube

[@ErikS-]

I have no issue with his accent. But stating he is doing this for free, is incorrect. A channel of 600k subs, earns quite a big buck.

[@s1ghtern]

I already finished this course when i commented. why would i ask for myself are you stpd. I commented this in everybodys behalf so its easier to understand in his future videos...

[@s1ghtern]

Ofc lets believe the subtitles are correct 👏👏👏😮‍💨

[@Maldiniiiiiii]

cihana selam bu videoyu izliyorsan bana ulaş .ALL ABOUT ELECTRONİC ADAMSIN