CombCkt - 21 - Gate Sizing for Large Circuits

[@pawansharma6226]

He is the best teacher. I literally spend 40-50 minutes watching his 25 min lecture. Initially I wasn't understanding Why he is not using Path delay Optimisation. BUT as I moved on in lecture, he throughly explains it... 🎉

[@Abhish1_7]

Anyone, please answer. Why that particular path is taken when sizing was not done?? 12:51 In the last example, sizing was available, so we got the critical path to be that one.

[@harshitprajapat2730]

I think that's what sir tried to explain that path sizing not scalable..... As there may be rise in path delay for some other path if if try to do so....

[@AbhishekSingh-up4rv]

26:36 How to solve for x1, x2, x3.......x7 using the given constraints?

[@akashekhar]

Search for convex optimization problems on youtube.

[@sayanbaidya9724]

mip package in python may be useful

[@socialogic9777]

23:37 a7 = a6 + d7

[@nityanand4581]

14:30 Increasing capacitance by factor of stage effort how ?

[@socialogic9777]

it's a concept of logical effort/stage effort, you can refer previous lectures.