Combinational Logic Design-II

[@faneeshbansal]

If we have stronger pmos, that means we will have high Noise margin low, because the noise margin low means range of values for which the input is considered as logic 0, and we know when the logic is 0, then the output is 1 i.e it will more in the favour of pmos ( pun). Same for nmos also, When stronger nmos , means vtc curve will shift to left side and we will have larger noise margin high.

[@shashwatrao6949]

Read the book after the lecture. I think , that will clear doubts

[@darpanbhalani4756]

isnt NM(low ) should be high instead of NM(high)??? ...bcz input low is extended .....so NM(low)=Vil-Vol...

[@sravanperakam5715]

yes sir is doing mistakes here and there....

[@rockingstone7700]

@@sravanperakam5715 yeahhh

[@dhruvandangar9972]

some time sir forgot it is one to zero or zero to one so please take care of it guys.

[@mohammadkhaliquekhan2041]

Sir is also a human don't try to become his teacher. 🙂