Combinational Logic Design-V

[@ankush9080]

Please correct sir width of PMOS =2 (w of NMOS ) sir, you said opposite

[@vbr87]

sir if VOL increases noise margin decreases or increases??

[@nitismishra551]

First sir was considering pull up is good but pull down not very strong. So Vol increases. NML =ViL- VoL So it decreases. Next in the graph he talked about circuit with weaker pull up. So VoH decreases. So VoH- ViH decrease and so NMH decrease. ViH ViL are same because they are signals from outside

[@dhanvinprajapati7049]

does DCVCL is useful for future ? the whole lecture goes above my head.....