Course : Systemverilog Verification 1 : L4.1: Arrays in Systemverilog

[@alvinaug3844]

sir, i think u have to use bit[3:0][7:0] byte;

[@SystemverilogAcademy]

You are right, at 3:06 it should have been an an array of size 3 as per the diagram, and so size should be be [3:0] not [2:0]. Thanks Alvin for this correction.

[@alvinaug3844]

@@SystemverilogAcademy thanks sir for ur great effort.Hopes u will update some lab section also with questa sim tool.It will be helpful for everybody.

[@SystemverilogAcademy]

Thanks, will try that :)

[@shreemit-travelvideosin4k550]

I also had the same doubt, hence came to comment section. Thanks Ajith Sir for the clarification.

[@tahirsengine]

Awesome lecture. Lush channel.

[@SystemverilogAcademy]

Thanks for the feedback !

[@bennguyen1313]

Not sure if there's a limit on the number of dimensions that can be synthesized to run on an FPGA.. but I'm having trouble with 3D. 2D seems to work fine.. I have a 32-bit ADC, that has 16 channels.. Libero doesn't seem to have any problem synthesizing a working bitstream, that declares and accesses the array: reg [ 31 : 0 ] adcData [ 15 : 0 ]; // 16 Channels, 32 bits each reg [ 31 : 0 ] reading; adcData [ channel ] [ 31 : 0 ]

[@SystemverilogAcademy]

Hi Ben, Sorry that I can't comment more on this as I need to spend some time to check the synthesis behaviour you describe.

[@krishnakittu6637]

Do more videos , helpfull

[@SystemverilogAcademy]

We will

[@108ahah]

agree! Thanks to @Systemverilog Academy

[@srinivasb4955]

Hi can you explain the packed and unpacked array in single array please

[@SystemverilogAcademy]

Hello, Not sure what exactly you are looking for. It'w common to use both packed & unpacked array declaration with a single variable. Eg: You wanted to use an array to store say 256 data packets in an array, where each packet is of 32 bit wide. The most common way to declare this array would be, logic [31:0] packet_arr[256];