Systemverilog | Test Bench Environment | Half Adder

[@sovietdog9998]

Amazing video. Your explanation of the overall test bench environment at the beginning helped tremendously in understanding each component.

[@vlsi_training3190]

Thanks 😊

[@andrewchiu886]

That is the best training material I had ever saw regarding the verification of the systemverilog

[@vlsi_training3190]

Glad you liked it!! Please help us to grow, like , subscribe and share!!

[@mathstar7516]

This video is a beginners masterclass expecting more videos from you 😊

[@ananditasrivastav7404]

this is what we call a perfect tutorial video. awesome explaination. crystal clear .

[@vlsi_training3190]

Glad! You liked it!

[@kishanbhojrath2755]

Understood the testbench flow, Well explained.

[@vanajachevuru4542]

Tha way of your explanation is Awesome ❤ thank you sir 🙏

[@sundramsingh2699]

This is a very nice video. everything is explained very nicely.

[@simrantomar5521]

very informative video, nicely explained

[@garimagautam1386]

Best resource available on KZbin for this topic

[@vlsi_training3190]

Thank you 😊

[@ayushtyagi9283]

Amazing explanation and very informative video sir.

[@artrgukt]

i can say "Excellent" and many thanks to you...do more

[@NehaVerma-jw7fm]

This video is relay help me to understand basic system verilog. Thank you sir :)

[@vlsi_training3190]

Thank you

[@mahmoodghorbanmoghaddam5641]

Thank you so much for your in-depth description. Hope to see your new video for sequential circuits in a bigger example.

[@vlsi_training3190]

Sure thing!

[@raghavchoudhary4630]

Thanks for explaining in such detail. Enjoyed watching it.

[@srinathk961]

thanks a lot bro, you make this complex concept into easiest way. you cleared all my confusions & doubt. i can't express my feeling now. thanks a lot sir.

[@vlsi_training3190]

glad, you liked it!

[@mughatoamugha9029]

Very smooth explanation.. please upload more videos sir.

[@lakshyasharma6972]

Bhai kya mst samjhya yar ... maza agya

[@parulrana2214]

Explained very well sir. If you are planning to upload more videos then, could you please make video on clocking block its importance and example.

[@shashvatmaurya6791]

Amazing explanation video

[@chyavanphadke4813]

This is just Awesome. Need more similar examples. Support is always there ..

[@vlsi_training3190]

Thank you!

[@reetikabanerjee1324]

Please upload more videos,it is really useful

[@godo1861]

Thank you very much ❤❤❤❤ this video was very clear and understable 👌👌👌 i wish if you can continue in a full terioral of system verilog because your way in explation is so good and clear 🌸🌸🌸

[@vlsi_training3190]

Please contact us on 8700965661.

[@rahulkatike6837]

This is a very well explained video that I have seen so far on this topic, please do some more videos with complicated examples by using reference model and monitor2... Thankyou...

[@vlsi_training3190]

Thanks, will do!

[@rahulkatike6837]

@@vlsi_training3190 eagerly waiting for your videos

[@mehulyadav730]

Keep it up. You are such good teacher. 👌👏👍

[@enamalatharun5182]

Very good explanation sir... Even for beginners it's clear to understand.. Thank you so much 🎉👏👏

[@vlsi_training3190]

Thank you for your input. If you need any classes you can write us on [e-mail]

[@Deva__clicks]

@@vlsi_training3190 why don't you continue

[@arp6900]

Awesomely explained !!

[@vlsi_training3190]

Thank you!!

[@vijaynayal9717]

very well explained .... appreciate your effort.....

[@vlsi_training3190]

Thank you!

[@vlsi_training3190]

For any training assistance please contact us on 8700965661

[@movieking314]

Thanks a lot. Please make these type of videos more.

[@vlsi_training3190]

sure

[@shikharathore6263]

Your explanation is very nice . Please upload more videos on SV and UVM

[@vlsi_training3190]

Sure shikha, will post remaining videos soon

[@balasubramanianr2238]

Very good flow of test bench environment

[@vlsi_training3190]

Thank you bala!

[@kaibalyakumarsahoo6655]

Very good explanation sir

[@BinhMinhNoiSach]

very good explanations thanks a lot

[@mounikachintapalli1011]

Hi sir, ur videos are very amazing. Please upload remaining videos sir. I'm requesting u sir please😊

[@aiyush5473]

Very Nice Video it really helped me in understanding environment. Plz make a verification environment for UART Protocol or I2C Protocol from basic

[@CallistoPili]

Is there any free tool available to use all of that? I cannot sell my car and my jewelry to just rent one of the tools for verification.

[@hiteshranjan4082]

now all things are clear thanku

[@khamerunnisa2677]

Very well explained..It was very useful for the beginners who are learning SV. Requesting a video regarding UVM test bench environment for similar example..

[@vlsi_training3190]

Sure! I will post it soon!

[@zahidfazal2176]

@@vlsi_training3190 when will your "soon" Pandey Ji. We are awaiting.

[@boodidasadguna1836]

Thanks alot Neeraj.. Awesome explanation.. Keep posting some other videos related to SV

[@rishabhkumarsoni1240]

wow, quiet a helpful explanation.

[@eslammorsie4908]

Much thanks for this awesome explanation 😃

[@vlsi_training3190]

Glad you liked it!! Keep supporting!!

[@ankamanirudh8837]

Sir, you very well explained thank you so much

[@vlsi_training3190]

You are most welcome

[@gunjanpandey2585]

Thanks alot for crystal clear vdo...i request you to cover more testbench scenarios like modport, clocking blocks,fifo Thanks in advance 🙂

[@ankushkumaryadav65]

really good video on system verilog

[@vlsi_training3190]

Thanks Ankush!

[@sabarish862]

Great video! Helped me a lot!

[@Ram_vlsi]

nice explanation..do more videos on uvm

[@rangaraoneelapala8823]

thank you sir making this lecture

[@shubhamroy5023]

just one word "WHOLESOME"

[@vlsi_training3190]

Thanks

[@moviesera5250]

FABULOUS BHAI

[@b-40pradoomrao4]

Best explanation 🔥🔥@vlsi_tranining please make totorial videos on System verilog + Projects on system verilog .

[@digambarbhole9467]

Nicely explained

[@gabbarjadhav2293]

thank you so much brother ...good explanation .......please check audio have less volume ...

[@gayathrishetty8799]

Amazing explanation, completely understood the process and communication. But can explain the clocking blocks and modports with example.

[@fasihuihassan518]

explained very well

[@ashokvatika2857]

Please make a test bench on uvm🙏🙏

[@vlsi_training3190]

Hi is it difficult to make video on UVM!! You can drop your query on [e-mail]

[@malikshanaah9804]

Amazing, Bro!

[@suchitrajaee8379]

A very nice explaination sir..you have clearly explained what each and every class do and what we have to write in that class..Can I get the the link of this code

[@shubhamsingh-me6hw]

sir make a video for clock ckt also, please(fifo)

[@Chill_TFO]

sir thank you very much , plz do make a video on uvm also

[@kittycatty335]

very helpful video!

[@saqibmansanu8423]

NYC BHAIYA ❤️❤️❤️

[@shirishtiwari8070]

Very good explain

[@sakshamsingh2005]

Thanks a lot. Helps a lot.

[@anusharamishetti8281]

Nice explanation sir . If it is possible can you upload sv environment for counters

[@ashijain2876]

Sir please upload more example of testbench verification of sv as well as uvm

[@spandanaka4764]

good explaination tq

[@madhanboddula9628]

So much useful

[@shubhamsingh-me6hw]

it's really helpfull...thanks sir

[@vlsi_training3190]

Glad to hear that Shubham!

[@peyyalapavani2401]

thank you so much sir

[@suchitrajaee8379]

can you explain us by taking a one bus protocol example in system verilog ,that how to use modport and clocking block

[@najlanajeeb]

well explained. could you add more examples/projects little bit complex one

[@vlsi_training3190]

Glad you liked it! For your query you can drop mail on [e-mail]

[@sonalkapila7398]

thanks....why did you declare input a, b specifically of 'bit' datatype, can we do it with 'logic' as well?

[@vlsi_training3190]

Yes please declare with logic only

[@hareeshkanchi6336]

can you do one simple code on uvm...your explanation is good so.pls

[@AkbarRajaei]

great tutorial. Is it necessary to use Mailbox? I have seen in some trainings like Xilinx and Doulos that they do not even talk about Mailbox.

[@vlsi_training3190]

no you can use queue also!! i hope they should be using queue if they are not using mailbox!

[@loyal8060]

Please upload more videos

[@omprakashpatel6322]

great work! keep doing it. Can do same with UVM taking half adder as an example?

[@soni8094]

sir,please do more videos on RTL verification and physical verification

[@ravirajac]

How monitor is generating Sum and Carry? I mean, where DUT is imported in Monitor to produce Sum, Carry?

[@shivanandajjannavar7934]

Sir, please start doing more videos on SV and UVM

[@vlsi_training3190]

please contact us on 8700965661

[@sahilagarwal6234]

thanks!!

[@perfectvips4587]

Your welcome Shahil

[@vlsi_training3190]

Your welcome shahil

[@manidipasamanta7853]

Thank You sir it is now fully cleared how a system verilog enviroment works with a simple code . But sir I have one doubt in the sv enviroment we have reference model also and for ref model do we have to write the code or it will be given by design engineers because we know that the ref model is a kind of duplicate of DUT

[@vlsi_training3190]

ref model is written by verification engineer!!

[@satheesh3210]

SIR PLEASE GIVE EXPLANATION ON ASYNCHRONOUS FIFO SV ENVIRONMENT

[@vipinpandey2225]

👍👍

[@ganauvm270]

can you upload asynchronous fifo verilog code and sv env

[@hemanthkumarsr9851]

excellent

[@vlsi_training3190]

Thanks

[@hemanthkumarsr9851]

Could you please upload any small uvm testbench like system verilog half adder

[@hemanthkumarsr9851]

Could you please share your email id

[@prince8441]

“Result is expected “ wasn’t printed…. May I know the reason? I am unable to understand the reason behind it not getting printed

[@akhilapp1135]

Sir please put videos on code coverage and functional coverage

[@vlsi_training3190]

Sure!

[@indiandrums8591]

please make a video of UVM tb

[@vlsi_training3190]

Sure I will make it!!

[@anushabudati868]

Sir , Please add more videos

[@madhavideshpande9660]

sir as earlier you told that the DUT will give the output & while making driver class you declare sum & carry . so who gives the output DUT or DRIVER class

[@vlsi_training3190]

Dut always gives output, we verify DUT only, reference model or scoreboard is having the same behavior like DUT, AND we compare dut and scoreboard logic

[@madhavideshpande9660]

@@vlsi_training3190 thank you sir can u make another video in which the modport is included

[@madhavideshpande9660]

sir can you put some lights on UVM verification environment. It's worked like blessing for me.

[@vlsi_training3190]

Sure will post soon!!

[@suryatejamedaramitta5306]

bro please do some more videos

[@vlsi_training3190]

What topic you are looking??

[@suryatejamedaramitta5306]

@@vlsi_training3190 I m looking for protocols

[@suryatejamedaramitta5306]

@@vlsi_training3190 I m looking for reference model checker

[@suryatejamedaramitta5306]

@@vlsi_training3190 golden model testbench

[@DeepakYadav-un4cv]

why we are not create trans in driver class.but in generator and monitor we are creating object.

[@vlsi_training3190]

Didn't get ur question, you can drop ur query on 8700965661!!

[@meghanas755]

Why we will use logic as input in dv test bench

[@vlsi_training3190]

any two state data type contains 0 and 1 value but for logic which is 4 state data type, it has 4 value , 0 1 ,x ,z . So sometimes we need to see that value 0 and 1 is getting generated in testbench for any variable or not. So for two state variable by default value will always b 0 so we can't say that test bench is generating that value. So if I will declare that variable by logic , whose by default value is x there we can see what value we are getting.

[@mughahotoyeptho1615]

hi sir, why did you used 3 ns delay at monitor ? if i remove dalay then there is an error so please reply to this question thank you

[@vlsi_training3190]

Here we are driving data at 0ns time from driver and that data is going to interface and then you are collecting that information in monitor, so I have used a small delay in monitor to make sure that data is sampled at monitor end. You might be ware with clocking block in sv, generally in interface we used that which gives the sampling information, you can reach me out at 9582148071 if you have any more issue

[@sandeepkumarravirala7028]

Please more examples sir

[@VijayaEligar]

please can u post some examples in UVM

[@vlsi_training3190]

sure will post it!

[@rangaraoneelapala8823]

sir try to do part 2 of system verilog please

[@vlsi_training3190]

You can reach us on [e-mail]

[@wicket4969]

Is this UVM?

[@vlsi_training3190]

No it's system verilog

[@mohdgufran4051]

why u are not writing reference model code in this example??

[@anilkumarkurra1314]

sir can you please tell me why we are only randomising only inputs ????

[@vlsi_training3190]

We want to test our design, lets say I want to verify and gate with Two input, so there will be four combination for 2 input and then there will be some output. Now suppose you have 8 input then the combination will be huge for input, and we can not write it manually. So we are declaring random keyword only for input for generating multiple input combination for a design, why we don't randomize output bcz when u will apply different input to design then it will produce some output, so we get output from design, that's why we don't randomize it!! I hope u got ur answer else u can write you doubt

[@anilkumarkurra1314]

@@vlsi_training3190 thank you so much sir

[@suryatejamedaramitta5306]

Bro do u have another channel

[@vlsi_training3190]

no I dont have another channel! will post more videos soon!