Creating a custom AXI-Streaming IP in Vivado

[@no5x937]

I've been following along your video and got to part of editing the custom IP (overwrite the generated code and replace it with alexforencich's verilog-axi code). However, Alex's GitHub page in 2022 looks very different than what is showing in your video. @ 4:30 you state that will post Alex's code below the video but it's not available here. Can you post this file and any other files required for this video so I can complete the lesson? Or can you provide a list of the current Github files on Alex's page? @8:00 you add the custom axis_fifo IP you created with Alex's edited HDL code. If I didn't edit Alex's code @ 4:30 and proceeded with all other changes, can I add this custom axis_fifo from the repository and modify its HDL code later if/when you provide it below? Or will I have to edit it @ 4:30 and proceed from there? Thank you, JT

[@fpgadeveloper]

Sorry for forgetting to add the code link to the video. You'll find the code in the blog post: www.fpgadeveloper.com/2017/11/creating-a-custom-axi-streaming-ip-in-vivado.html/

[@lukel4662]

Thank you for your explanation and let me know a lot about axi stream. It would be better if you could explain the code you changed

[@jayatidutta1941]

Inspite of following every steps...I am getting the error of "ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source: /axi_dma_0/m_axi_sg_aclk"...but I have used a clock(sim_clk_gen) already there and all the clk ports are connected....how the issue can be resolved?

[@jayatidutta1941]

btw...I am using ZCU102 board

[@prithvivelicheti287]

thank you.

[@Sashachacka]

Can you share the code please?

[@rjuez00]

he did not, in fact, post the link below the video 😂😂😂😂😂😂

[@jajajaj666]

Excellent