How to create a custom PYNQ overlay

[@rohankalbag5541]

Very helpful and intuitive explanation, thanks a lot

[@abuali5513]

Greater video. Thank you

[@thanatosor]

Make the algorithm in HLS/C then add to Vivado as IP Design, finish the block then export/generate BitStream to be called in Overlay.

[@Ribbles22]

Why did vivado add the AXI interconnect? Is that because adder.cpp pragma is set to use INTERFACE s_axilite?

[@europeanunion5765]

11:10 it seems you need the .hwh file as adder.hwh from the hw_handoff subfolder next to the bitstream file on your pynq, otherwise the pynq will show an error message that it cannot locate the bitstream

[@陳立勝-z3i]

after generate bitstream, File>Export>Export Hardware then you can get the .xsa file that include the .hwh file

[@MichalMonday]

That's very useful, thanks.

[@swery11]

Is it the same if I use this as it is in vitis?