Current Mirror Layout - English Version

[@vatsala900]

Thanks a lot, Sir ... You are trying to help lots of students by providing the best Analog layout design contents 🙏

[@rajkumarpatidar8361]

It is really very useful, Thank you sir for explaining Current mirror.

[@ximingfu1426]

You are giving me very valuable information, that is fanstastic!!!!, thank you very much

[@analoglayout]

Thx buddy

[@moin4453]

Very nice video. Can you please make a video of CM with the common centroid method? Thanks in advance.

[@mokong2627]

do you already have videos for modgen for CM and DIFF PAIR? and also video for mpp for creating shields? thanks for the video :-)

[@jovandrum21]

I think the layout will be easier if you don't use the multiplier and just fingers since you are merging the diffusions anyway.

[@mohammedafzal534]

Good explanation with practical sir

[@shashankgowda1139]

the layout that you are doing is for understanding how it is connected...but if you take all theoretical concepts consideration then you do it in a different way right?

[@analoglayout]

Ofcourse , we have calculat em / ir / signal integratity so on ... Every thg we have consider before routing

[@venkatasaikarthikvaranasi7303]

Can you please made a video which explains ... only "SHORTCUTS in CADENCE LAYOUT" Do it as soon as possible...

[@analoglayout]

sure ...

[@3RiversSQ]

Could you explain why diode connected transistor in current mirror sit in between and other devices side by side. Means you have done the AABBAA. BB= diode connected.

[@analoglayout]

From that diode only current is mirroring , so only always we have keep diode middle ....

[@tanmoygupta8212]

Sir in the current mirror circuit, gate and source has been shorted. It should be gate and drain. Anyways splendid work sir. Helpful

[@analoglayout]

It's not a real time circuit , jusr a example , so Conny the terminal in a proper way or which is correct .

[@kitchwatembo]

Doesn't matter, MOSFET is bidirectional. Simulate it and you will see it works!

[@jangteddy1798]

Sir could you share how to layout the cuurent bias of "folded cascode amp" ?

[@MALAYAPH24]

Awesome.thanks so much sir

[@sv5144]

Why source and drain Should be merged..?..in schematic where it is showing

[@analoglayout]

Without merging also we can do, but this will create od etching issue, sti, area waste, etc

[@k.subashsubash6251]

Sir how did you say BBAABB is the best matching.There will be a other possibilities also for matching.

[@analoglayout]

as a layout engineer , we cant able say the best pattern , we will get the pattern from circuit design engineer based on that we have do matching , here for E.g i said aabbaa is the best pattern

[@myviews8991]

For current mirror , we use common centroid matching , why interdigitization was done in this video?

[@94D33M]

This is common centroid too. Both A and B have the same common point.

[@kamalprasad3293]

can you please explain why not to use common centroid pattern for current mirror ?

[@analoglayout]

You can use

[@94D33M]

This is also current mirror since the middle point of both devices are at the center.

[@tanuja8745]

how can we draw layout of current mirror in interdigitation matching if we have multiplier = 1 and fingures = 4 ... and what is the matching pattern ?

[@analoglayout]

How will design current mirror with only 1 device ? We need min 2 devices

[@gomnickim2452]

Thank you for the awesome video. It really helped me a lot. I was just wondering about all the bodies for mosfets from that current mirror. Is it okay not to generate and route body for every individual mosfet?

[@analoglayout]

Have to generate manually

[@sushantsharma180]

sir do some lecture on floor planning matching

[@analoglayout]

analog floor plan or physical design floor-plan

[@sushantsharma180]

@@analoglayout floor plan

[@sushantsharma180]

sir match the transistor when you have only schematic

[@analoglayout]

sure

[@meghakg6283]

Sir, how are you saying Drain and source should be merged? I don't get that part, please reply.

[@analoglayout]

Mention the time spot, where I've mentioned

[@meghakg6283]

@5:20 sir

[@sv5144]

Please clear this doubt

[@nagendrababumoodu2583]

Super Sir

[@avinashpurohit7401]

nice

[@StayInBliss]

thanks

[@eng.gilp.ramasececms7448]

Is this 180 nm technology?

[@analoglayout]

65tsmc RF

[@eng.gilp.ramasececms7448]

@@analoglayout Thank you

[@kazz7148]

complete nonsense schematic

[@analoglayout]

I'm not a circuit designer .... Anyway

[@zilantong548]

Can you please made a video which explains ... only "SHORTCUTS in CADENCE LAYOUT" Do it as soon as possible...