It's not that we can just pass our semester exams with ur lectures ..... it's all GATE level content that u r teaching for free👏👏👏 Hat's off to u sir
@nathan55087 жыл бұрын
i learnd more stuff in a 9min video than a 90min lecture
@owaiswasim89115 жыл бұрын
rather 4.5 min at 2x speed
@DilshanMarasinghe5 жыл бұрын
I feel you..
@lorddani73005 жыл бұрын
same man this is excuse i gave to my family when they ask why you arent going university
@srinuvasdukka5822 Жыл бұрын
@@owaiswasim8911 🤣
@yusuf_f_f_f Жыл бұрын
I wish this guy could cover all of my undergrad degree because his videos are much better than 90 min lectures
@engineersspace93572 жыл бұрын
I just clapped with joy at the end. 👏👏 You cannot imagine how fast I understood everything after watching this video...I just enlightened my class knowledge 100 times! The best Electronic course tutorials are here my fellow engineers.
@rahulkhandelwal87818 жыл бұрын
sir its only because of ur videos i cleared my exam..thnx a lot..keep it up
@shauryasingh0076 жыл бұрын
hopefully +1
@DilshanMarasinghe5 жыл бұрын
U JUST SAVED MY LIFE THIS SEMESTER
@aayushichawla8 жыл бұрын
Thank you so much for all the DE videos...they helped me score really good in my finals...
@wasiqazmi15288 ай бұрын
tommorow is my dld exam.hoping to get good marks because of your videos.
@prasadnaik34565 жыл бұрын
Heroes fight for their people from behind their masks. Neso Academy fights for students from behind an electronic board.
@bijivemulasairakeshreddy47394 жыл бұрын
not a suitable dialogue
@vermatushant4 жыл бұрын
good try 🤣
@susheelapatgar36402 жыл бұрын
😁 benki🔥
@Hurricoaster8 жыл бұрын
Wow! With this knowledge, the possibilities are endless. Imagine, instead of clearing each flip flop's state to zero, you use the same NAND gate but connect it to PST and CLR on each FF in a different way. You could manipulate this to use counters to skip to different values
@jamalansari14627 жыл бұрын
its my exam today and at 3:00 am I am listening to your lecture ......... thnks sir
@ashwinbahadur67885 жыл бұрын
And me at 5:00 am
@turtlepedia51494 жыл бұрын
M1 at 237
@tavvagnrsnprudhvith53226 жыл бұрын
Thank You So much Sir...it's just because of you i am able to understand Digital Logic circuits course which is in my present semester.
@shrashtisharma44597 жыл бұрын
sir ur lectures are truly worth it gave me great understanding . sir i also want a lecture on how to design a counter which have only the even states.
@devashishpatel54387 жыл бұрын
Your lectures are really amazing sir ! I used to hate this subject before I watched ur videos ! Atleast now I am comfortable with it !
@cmac1600 Жыл бұрын
I wish I found your videos sooner. This helped me so much thank you so much for making these videos
@snehashishbanerjee25753 жыл бұрын
Can't appreciate your amazing explanation enough! Just a simple correction- I think (at 7:55) the signs of the NOT gates should be mirrored, for Qc and Qa. Correct me if m wrong here...!
@shubhranginidas6818 Жыл бұрын
Yup that's correct!
@prashantsingh7372 Жыл бұрын
@@shubhranginidas6818 ohh wow u r clearing his doubt after 1 year
@subhashinia14143 жыл бұрын
Your videos are really great. Thank you so much. I cleared my exams with good grade.
@sdutta58612 жыл бұрын
I was struggling for 3 hours with a problem. Thank God I watched this video! One minute into the video and ta-da ! Problem solved. :)
@stanleybane54834 жыл бұрын
Now I'm confident about my interns. Thank you
@ritikbisht24887 жыл бұрын
All the lecturers r awesome...I had cleared all my doubts.... specially I liked the flip flops lectures the most.... thanks a lot to neso academy
@JustLikeRAV8 жыл бұрын
Thank you sir, you have exceptional teaching skills!
@nisargsheth98417 жыл бұрын
Sir, you should also mention that we are observing Q as the output...(in the neg-pos edge triggered section in the beginning of the video). And thank you very much for such great videos..appreciate your effort!
@fatamajannattisha685 жыл бұрын
i don't have any words to thank u
@arjungautam45426 жыл бұрын
Thanks Neso i learnt better than 1 hr lecture in college #from #Nepal
@rajeevangunasekaran85407 жыл бұрын
all your lectures are superb sir. thanks a lot!!
@nmn0021 күн бұрын
Woww my favorite channel Thank you so much❤
@meKinzaKhan7 жыл бұрын
thank you so much sir these videos are so much helpful
@AnandKumar-xi8qu8 жыл бұрын
you drew the NOT gate symbol in the wrong direction
@realme-xv1jf Жыл бұрын
thanks this qs came in exam but with a twist qs was design a ripple decade counter using jk ff without clr and preset signals
@FarhanKhan-yl9nn6 жыл бұрын
man you are awsummm.. thanx alott fr videos.. bhot duaa milega humlog ka.. God bless
@mohammedhammad42723 жыл бұрын
The besttt teacher ever
@rishabhjain24427 жыл бұрын
bache ki jaan bachali apne bauji ,dhanyawad :))
@arjungautam45426 жыл бұрын
Thanks sir .Watching from Nepal
@samriddhijain16514 жыл бұрын
In my book it says to draw kmap for output states then draw circuit for clear input. Here we are taking just the first invalid state
@yonghuiliew80664 жыл бұрын
Thank you for the important notes in the beginning of the video. That's what the lecturer did not explain which confused everyone LOL
@tonnykilama99118 жыл бұрын
the lectures are very interesting, THANKYOU very much for the videos
@SaugatBaral2 жыл бұрын
Thank You Very Much! Your videos have helped me alot.
@ayushmishra12964 жыл бұрын
A small Mistake is that when using CLEAR (Qd,Qc,Qb,Qa)=0 then when you are using NAND gate inputs should not be Qd and Qb instead Qd NOT And Qb NOt.
@Pushpa18077 жыл бұрын
Good morning sir. You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs. Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately? Am I missing something? Thank you for the lectures.
@rushivachhani86155 жыл бұрын
same question
@InspiringInsightsbyprajjaldhar3 жыл бұрын
They are asynchronous so output will not wait for next trigger and went off
@shreeyapatel76486 жыл бұрын
The first part of the video created a great confusion for me As you had used negative edge triggered FF to make a down counter where Q was the input and Q' was used as clock But as you did not mention here in this video that you considering Q as the output for all....It made me think for a very long while. Hope this comment helps someone else too.
@anmol34579 ай бұрын
i suppose he did not mention it here because he's mentioned it in the previous 3/4 bit async UP counter videos.
@sam-pd6zi2 жыл бұрын
thanks, now i am understanding the working of computer
@Dr.SahadevRoy5 жыл бұрын
At time 7:11Not gate symbol is reversed and also 7:21 is also reversed. Explanation is very good.
@ishikamehra58536 жыл бұрын
Thank you so much sir Your videos helps me alot
@dhananjay94938 ай бұрын
number 1 content.
@adityatanmay4 жыл бұрын
earlier in down counter video, you used negative edge triggered and Q as clock, you have not mentioned that in this lecture?
@infogalaxy83182 жыл бұрын
It is indeed a fabulous lecture ..which content clear ...but only one correction at the en d..for the two input nand gate you must take qc and qa as 1 nand 1 is 0 but in the lecture the two inputs are qd and qb whose nand is 1 and clr would be 1 ..And sorry for poiniting out such a silly mistake for a great lecture . And shouldnt we stop at 1001 and not at 1010 , because 1010 might also be printed , becoz we are print qd,qc , qb, qa? Correct me if I am wrong
@rushivachhani86155 жыл бұрын
You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs.
@nilouboe50965 жыл бұрын
That is exactly my question i think the number 10 would also be displayed since we have 1010 before resat???!!
@tiktik15165 жыл бұрын
Pakka explanation..... awesome.thank you sir
@rajdeva45764 жыл бұрын
Tqs bro u helped me my exam will start 10:00 clock
@ghazikhan26245 жыл бұрын
Great
@kamanianirudh51574 жыл бұрын
What do you mean by (MN) wheather M*N or simply MN at the time of cascading the counters??
@kamyarathod57025 жыл бұрын
This is very helpful.Thank you sir
@nalwayaadi8 жыл бұрын
Thank you so much sir. Your videos have be very helpful in my studies. It's just that we cannot find any serial order in your videos which makes it difficult to find which video is next. If you could add a serial order in your videos it would be very helpful.Thank you.
@celalyahyaergun76144 жыл бұрын
you are a gift from the god to us
@sumitshekhar059 жыл бұрын
sir, if we use +ve edge triggered clock then what about race around condition ?? you taught that to overcome race around condition we use -ve edge triggering .
@saifkhanali18 жыл бұрын
+sumit shekhar LPC
@chandrashekar-ei2zg5 жыл бұрын
It takes place in level triggering
@chandrashekar-ei2zg5 жыл бұрын
To overcome it we use 3 methods 1)(T/2)>FF propagation delay 2) edge triggering and 3) master slave JK flip flop
@aakashtungariya72798 жыл бұрын
awesome lectures sir
@lovicabod5606 Жыл бұрын
great jop sir that's amazing
@ferociousbilkenter44683 жыл бұрын
Sir, since we do not want 1010 to appear as the output, shouldnt we feed 1001 as the input of the NAND gate? If we reset after seeing 1010 output, dont we somehow count from 0000 to 1010?
@nikosathanasopoulos5257 Жыл бұрын
Yes we will in fact see for a short period of time 1010 as the output. To solve this problem we can connect the Clock-Enable input of the 4th Flip Flop with the output Qa of the first flip flop. Then we need to connect the J input of the 4th Flip Flop to an AND gate of Qb and Qc. As a result the Qd changes state only when Qa drops from 1 to 0 and Qb=Qc=1and resets to 0 when Qa drops from 1 to 0 every other time (J=0,K=1) .
@shibajisahu31044 жыл бұрын
As clear is active low signal so it will work when clr=1 because when clr=1 then input to ff from clr =0 and output=0 So according to this concept the output of the nand gate should =1 to active the clr input but you are doing opposite to this? Please clear my doubt Am I wrong or you taught wrong?
@rajeshpadhy97178 жыл бұрын
for positive edge triggered FF the race around condition will appear.How could it be used as counter?could you please explain.
@yoyoking6065 Жыл бұрын
Nice explanation
@Anilkumar-xg2dh4 жыл бұрын
Excellent logic bhayyaa
@GSKHappyLearning3 жыл бұрын
Thank you for best teachings... 1 question : why not to use and gate instead of nand gate?
@susmithatalupula97912 жыл бұрын
What type of counter do we get if flip flops include both negative and positive triggered flip flops
@pinkisuthar64212 жыл бұрын
You really work hard, I'm worried because I clear concept here but what about semester exam we've to write more and how will we write because we don't have content?
@kanchangupta30416 жыл бұрын
These videos are really appreciating but in BCD counter we have to use truth table and k - maps while making the mod 10 counters.
@SivaKumar-op3wk6 жыл бұрын
it is very easy method for all ece students
@johnbrianalmazan65224 жыл бұрын
is that up/down? or is it just up counter?
@TRAVEL_MAHARASHTRA_AJ7 жыл бұрын
he give 2 clock inputs a and b ,,output of 1st flip flop not given to second as clock,,he gives 2nd input to second flip flop and then ckt is similar,,an logic used that is also different
@TRAVEL_MAHARASHTRA_AJ7 жыл бұрын
sir pls i have doubt about it,,is it ic 7490 ripple counter,,because when I reffer ic 7490 ripple counter internal diagram it's seems like little different from u mentioned in video pls suggest fast i have exams 2 days after
@surajchikne50986 жыл бұрын
Ty sir for videos !!! This saved my life .
@tasneemtasneem7239 Жыл бұрын
Thanks for your help
@prainamalik23249 жыл бұрын
BCD counter is the part of synchronous counter by m.morris mano(digital logic and computer design) but you say it is the part of asynchronous counter. so i want to know which is real???????? plzzz tell
@gnanyreddy30308 жыл бұрын
+Praina Malik arey sir in this presentation explained bcd ripple counter , which is asynchronous.But there is also synchronous bcd counter.I too follow m.morris book
@shubhamsatle81446 жыл бұрын
Praina Malik Bcd counter has both forms asynchronous as well as synchronous,both are correct
@sridharch19482 жыл бұрын
Excellent 👍
@jatayubaxi45532 жыл бұрын
Excellent.
@kesinenisireesha77999 жыл бұрын
U r great sir....
@mathewgeorge36736 жыл бұрын
So for ripple counters, all we need to do is determine the number of states we have in the count sequence and then attach the clocks according to the type of edge trigger? Do we use synchronous counters to implement the circuitry for sequences that skip states like 0, 1, 2, 4, 6?
@yjklmnop Жыл бұрын
Yes we use synchronous counters to implement the circuitry for sequence that skips states
@premsudheer20927 жыл бұрын
good explination man..
@theodorekoussoulis77332 жыл бұрын
I am 62 years old and I follow digital design as a hobby.I want make a JK FF counter that gives the sequence 10,22, 5.4.3. I have seen a lot of your interesting videos but I cannot figure out how to do it. Can you give me a hand ? Theodore from Greece.
@sinto41055 жыл бұрын
in 2:09 when you are discussing positive edge trigger you are telling about the clock but not about the output clear from where you are taking the output when positive edge triggring
@krishnaraomantha88997 жыл бұрын
thank you.........this helped me a lot really!!😉😃
@sahidahamed20533 жыл бұрын
Why all ff circuites are in negative edge triggering? Any reason
@russellandrady2 жыл бұрын
Someone - Hei. What is your campus? My mind - Neso academy
@SaipraveenSeva7 жыл бұрын
if we place positive edge trigger how can it be JK flipflop??
@snssatyabhagavan3 жыл бұрын
Why we are restricting to 10 when we are having chance up to count 16.
@josiahvanrooyen77397 жыл бұрын
Hello, if I have a asynchronous/ripple D flip-flop counter with a count sequence of 10, 9, 8, 7, 6, 5, 4, 3 and repeat but with provition for a logic 0 output on 8 and a logic output on 6, how exactly would I go about with this kind of a question. I understand that I will use the positive egde triggered and Q would be the clock. I would the connect the NAND gate with input 3 to clear to ensure that it will repeat the sequence but what of the provitions and would the sequence start at 15 and go down or would I also need to connect a NAND gate to PRE so it starts at 10. Any help would be much appreciated.
@mariahh20345 жыл бұрын
i understand why we removed Qa and Qc but how did we know they are not gate?
@hunain578 жыл бұрын
MAN YOU ROCK!!!!!
@sriparno11464 жыл бұрын
At 7:13 minute of the video why did you put the value of Qc and Qa by using a inverted NOT gate and taking the value to NAND Gate
@KingTsunamy7 жыл бұрын
That means the counter is modulo 10 or modulo 9?
@krishnabitling24476 жыл бұрын
Why cant we use Qa and Qc
@sayan4866 жыл бұрын
7:11. Why NOT gates are placed in reverse manner for Qc & QA?
@Ali-xy9fi3 жыл бұрын
What is the equations for j, k input? Because if i apply k-map the answers are different then =1
@nainaagrawal83143 жыл бұрын
In cascading maximum count will be MN - 1 or (M - 1)(N - 1)?
@nusratjahan96976 жыл бұрын
Can you explain any explain in which clear is applied to particular filp flop.. Eg if 4ff are there and in only 2ff clear is used.
@vasumahajan64075 жыл бұрын
Where r we taking the output in cases mentioned in the starting of the video
@anusharapaka24134 жыл бұрын
Output is same Qa Qb Qc Qd But there due to 1010 -10 1 should convert to 0 so nand gate is used for Qd Qb in this case Dacade is for 0-9 decimals
@theross3278 жыл бұрын
do u have the decade down counter? from 9 to 0. how to make the count start at 9, not at 15?
@learn_what_I_learn7 жыл бұрын
Sir, but you used Q as clock in the down counter too. Then why did you say to use Q complement as clock.
@nilouboe50965 жыл бұрын
in that case you have to use Q complement as an output if you use Q an clock in down counter. its more convenient to stick with one output(Q) and just change the clock form Q to Q complement to switch between up and down counter.
@amitbajpai84917 жыл бұрын
Is there any difference between MOD 10 asynchronous counter and decade counter
@bharathlr67395 жыл бұрын
Both are same
@ushoshibera75616 жыл бұрын
If the preset is not connected then will it affect the circuit??