Decade (BCD) Ripple Counter

[@swapnasruji.9933]

It's not that we can just pass our semester exams with ur lectures ..... it's all GATE level content that u r teaching for free👏👏👏 Hat's off to u sir

[@nathan5508]

i learnd more stuff in a 9min video than a 90min lecture

[@owaiswasim8911]

rather 4.5 min at 2x speed

[@DilshanMarasinghe]

I feel you..

[@lorddani7300]

same man this is excuse i gave to my family when they ask why you arent going university

[@srinuvasdukka5822]

@@owaiswasim8911 🤣

[@yusuf_f_f_f]

I wish this guy could cover all of my undergrad degree because his videos are much better than 90 min lectures

[@engineersspace9357]

I just clapped with joy at the end. 👏👏 You cannot imagine how fast I understood everything after watching this video...I just enlightened my class knowledge 100 times! The best Electronic course tutorials are here my fellow engineers.

[@rahulkhandelwal8781]

sir its only because of ur videos i cleared my exam..thnx a lot..keep it up

[@shauryasingh007]

hopefully +1

[@DilshanMarasinghe]

U JUST SAVED MY LIFE THIS SEMESTER

[@aayushichawla]

Thank you so much for all the DE videos...they helped me score really good in my finals...

[@wasiqazmi1528]

tommorow is my dld exam.hoping to get good marks because of your videos.

[@prasadnaik3456]

Heroes fight for their people from behind their masks. Neso Academy fights for students from behind an electronic board.

[@bijivemulasairakeshreddy4739]

not a suitable dialogue

[@vermatushant]

good try 🤣

[@susheelapatgar3640]

😁 benki🔥

[@Hurricoaster]

Wow! With this knowledge, the possibilities are endless. Imagine, instead of clearing each flip flop's state to zero, you use the same NAND gate but connect it to PST and CLR on each FF in a different way. You could manipulate this to use counters to skip to different values

[@jamalansari1462]

its my exam today and at 3:00 am I am listening to your lecture ......... thnks sir

[@ashwinbahadur6788]

And me at 5:00 am

[@turtlepedia5149]

M1 at 237

[@tavvagnrsnprudhvith5322]

Thank You So much Sir...it's just because of you i am able to understand Digital Logic circuits course which is in my present semester.

[@shrashtisharma4459]

sir ur lectures are truly worth it gave me great understanding . sir i also want a lecture on how to design a counter which have only the even states.

[@devashishpatel5438]

Your lectures are really amazing sir ! I used to hate this subject before I watched ur videos ! Atleast now I am comfortable with it !

[@cmac1600]

I wish I found your videos sooner. This helped me so much thank you so much for making these videos

[@snehashishbanerjee2575]

Can't appreciate your amazing explanation enough! Just a simple correction- I think (at 7:55) the signs of the NOT gates should be mirrored, for Qc and Qa. Correct me if m wrong here...!

[@shubhranginidas6818]

Yup that's correct!

[@prashantsingh7372]

@@shubhranginidas6818 ohh wow u r clearing his doubt after 1 year

[@subhashinia1414]

Your videos are really great. Thank you so much. I cleared my exams with good grade.

[@sdutta5861]

I was struggling for 3 hours with a problem. Thank God I watched this video! One minute into the video and ta-da ! Problem solved. :)

[@stanleybane5483]

Now I'm confident about my interns. Thank you

[@ritikbisht2488]

All the lecturers r awesome...I had cleared all my doubts.... specially I liked the flip flops lectures the most.... thanks a lot to neso academy

[@JustLikeRAV]

Thank you sir, you have exceptional teaching skills!

[@nisargsheth9841]

Sir, you should also mention that we are observing Q as the output...(in the neg-pos edge triggered section in the beginning of the video). And thank you very much for such great videos..appreciate your effort!

[@fatamajannattisha68]

i don't have any words to thank u

[@arjungautam4542]

Thanks Neso i learnt better than 1 hr lecture in college #from #Nepal

[@rajeevangunasekaran8540]

all your lectures are superb sir. thanks a lot!!

[@nmn00]

Woww my favorite channel Thank you so much❤

[@meKinzaKhan]

thank you so much sir these videos are so much helpful

[@AnandKumar-xi8qu]

you drew the NOT gate symbol in the wrong direction

[@realme-xv1jf]

thanks this qs came in exam but with a twist qs was design a ripple decade counter using jk ff without clr and preset signals

[@FarhanKhan-yl9nn]

man you are awsummm.. thanx alott fr videos.. bhot duaa milega humlog ka.. God bless

[@mohammedhammad4272]

The besttt teacher ever

[@rishabhjain2442]

bache ki jaan bachali apne bauji ,dhanyawad :))

[@arjungautam4542]

Thanks sir .Watching from Nepal

[@samriddhijain1651]

In my book it says to draw kmap for output states then draw circuit for clear input. Here we are taking just the first invalid state

[@yonghuiliew8066]

Thank you for the important notes in the beginning of the video. That's what the lecturer did not explain which confused everyone LOL

[@tonnykilama9911]

the lectures are very interesting, THANKYOU very much for the videos

[@SaugatBaral]

Thank You Very Much! Your videos have helped me alot.

[@ayushmishra1296]

A small Mistake is that when using CLEAR (Qd,Qc,Qb,Qa)=0 then when you are using NAND gate inputs should not be Qd and Qb instead Qd NOT And Qb NOt.

[@Pushpa1807]

Good morning sir. You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs. Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately? Am I missing something? Thank you for the lectures.

[@rushivachhani8615]

same question

[@InspiringInsightsbyprajjaldhar]

They are asynchronous so output will not wait for next trigger and went off

[@shreeyapatel7648]

The first part of the video created a great confusion for me As you had used negative edge triggered FF to make a down counter where Q was the input and Q' was used as clock But as you did not mention here in this video that you considering Q as the output for all....It made me think for a very long while. Hope this comment helps someone else too.

[@anmol3457]

i suppose he did not mention it here because he's mentioned it in the previous 3/4 bit async UP counter videos.

[@sam-pd6zi]

thanks, now i am understanding the working of computer

[@Dr.SahadevRoy]

At time 7:11Not gate symbol is reversed and also 7:21 is also reversed. Explanation is very good.

[@ishikamehra5853]

Thank you so much sir Your videos helps me alot

[@dhananjay9493]

number 1 content.

[@adityatanmay]

earlier in down counter video, you used negative edge triggered and Q as clock, you have not mentioned that in this lecture?

[@infogalaxy8318]

It is indeed a fabulous lecture ..which content clear ...but only one correction at the en d..for the two input nand gate you must take qc and qa as 1 nand 1 is 0 but in the lecture the two inputs are qd and qb whose nand is 1 and clr would be 1 ..And sorry for poiniting out such a silly mistake for a great lecture . And shouldnt we stop at 1001 and not at 1010 , because 1010 might also be printed , becoz we are print qd,qc , qb, qa? Correct me if I am wrong

[@rushivachhani8615]

You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs.

[@nilouboe5096]

That is exactly my question i think the number 10 would also be displayed since we have 1010 before resat???!!

[@tiktik1516]

Pakka explanation..... awesome.thank you sir

[@rajdeva4576]

Tqs bro u helped me my exam will start 10:00 clock

[@ghazikhan2624]

Great

[@kamanianirudh5157]

What do you mean by (MN) wheather M*N or simply MN at the time of cascading the counters??

[@kamyarathod5702]

This is very helpful.Thank you sir

[@nalwayaadi]

Thank you so much sir. Your videos have be very helpful in my studies. It's just that we cannot find any serial order in your videos which makes it difficult to find which video is next. If you could add a serial order in your videos it would be very helpful.Thank you.

[@celalyahyaergun7614]

you are a gift from the god to us

[@sumitshekhar05]

sir, if we use +ve edge triggered clock then what about race around condition ?? you taught that to overcome race around condition we use -ve edge triggering .

[@saifkhanali1]

+sumit shekhar LPC

[@chandrashekar-ei2zg]

It takes place in level triggering

[@chandrashekar-ei2zg]

To overcome it we use 3 methods 1)(T/2)>FF propagation delay 2) edge triggering and 3) master slave JK flip flop

[@aakashtungariya7279]

awesome lectures sir

[@lovicabod5606]

great jop sir that's amazing

[@ferociousbilkenter4468]

Sir, since we do not want 1010 to appear as the output, shouldnt we feed 1001 as the input of the NAND gate? If we reset after seeing 1010 output, dont we somehow count from 0000 to 1010?

[@nikosathanasopoulos5257]

Yes we will in fact see for a short period of time 1010 as the output. To solve this problem we can connect the Clock-Enable input of the 4th Flip Flop with the output Qa of the first flip flop. Then we need to connect the J input of the 4th Flip Flop to an AND gate of Qb and Qc. As a result the Qd changes state only when Qa drops from 1 to 0 and Qb=Qc=1and resets to 0 when Qa drops from 1 to 0 every other time (J=0,K=1) .

[@shibajisahu3104]

As clear is active low signal so it will work when clr=1 because when clr=1 then input to ff from clr =0 and output=0 So according to this concept the output of the nand gate should =1 to active the clr input but you are doing opposite to this? Please clear my doubt Am I wrong or you taught wrong?

[@rajeshpadhy9717]

for positive edge triggered FF the race around condition will appear.How could it be used as counter?could you please explain.

[@yoyoking6065]

Nice explanation

[@Anilkumar-xg2dh]

Excellent logic bhayyaa

[@GSKHappyLearning]

Thank you for best teachings... 1 question : why not to use and gate instead of nand gate?

[@susmithatalupula9791]

What type of counter do we get if flip flops include both negative and positive triggered flip flops

[@pinkisuthar6421]

You really work hard, I'm worried because I clear concept here but what about semester exam we've to write more and how will we write because we don't have content?

[@kanchangupta3041]

These videos are really appreciating but in BCD counter we have to use truth table and k - maps while making the mod 10 counters.

[@SivaKumar-op3wk]

it is very easy method for all ece students

[@johnbrianalmazan6522]

is that up/down? or is it just up counter?

[@TRAVEL_MAHARASHTRA_AJ]

he give 2 clock inputs a and b ,,output of 1st flip flop not given to second as clock,,he gives 2nd input to second flip flop and then ckt is similar,,an logic used that is also different

[@TRAVEL_MAHARASHTRA_AJ]

sir pls i have doubt about it,,is it ic 7490 ripple counter,,because when I reffer ic 7490 ripple counter internal diagram it's seems like little different from u mentioned in video pls suggest fast i have exams 2 days after

[@surajchikne5098]

Ty sir for videos !!! This saved my life .

[@tasneemtasneem7239]

Thanks for your help

[@prainamalik2324]

BCD counter is the part of synchronous counter by m.morris mano(digital logic and computer design) but you say it is the part of asynchronous counter. so i want to know which is real???????? plzzz tell

[@gnanyreddy3030]

+Praina Malik arey sir in this presentation explained bcd ripple counter , which is asynchronous.But there is also synchronous bcd counter.I too follow m.morris book

[@shubhamsatle8144]

Praina Malik Bcd counter has both forms asynchronous as well as synchronous,both are correct

[@sridharch1948]

Excellent 👍

[@jatayubaxi4553]

Excellent.

[@kesinenisireesha7799]

U r great sir....

[@mathewgeorge3673]

So for ripple counters, all we need to do is determine the number of states we have in the count sequence and then attach the clocks according to the type of edge trigger? Do we use synchronous counters to implement the circuitry for sequences that skip states like 0, 1, 2, 4, 6?

[@yjklmnop]

Yes we use synchronous counters to implement the circuitry for sequence that skips states

[@premsudheer2092]

good explination man..

[@theodorekoussoulis7733]

I am 62 years old and I follow digital design as a hobby.I want make a JK FF counter that gives the sequence 10,22, 5.4.3. I have seen a lot of your interesting videos but I cannot figure out how to do it. Can you give me a hand ? Theodore from Greece.

[@sinto4105]

in 2:09 when you are discussing positive edge trigger you are telling about the clock but not about the output clear from where you are taking the output when positive edge triggring

[@krishnaraomantha8899]

thank you.........this helped me a lot really!!😉😃

[@sahidahamed2053]

Why all ff circuites are in negative edge triggering? Any reason

[@russellandrady]

Someone - Hei. What is your campus? My mind - Neso academy

[@SaipraveenSeva]

if we place positive edge trigger how can it be JK flipflop??

[@snssatyabhagavan]

Why we are restricting to 10 when we are having chance up to count 16.

[@josiahvanrooyen7739]

Hello, if I have a asynchronous/ripple D flip-flop counter with a count sequence of 10, 9, 8, 7, 6, 5, 4, 3 and repeat but with provition for a logic 0 output on 8 and a logic output on 6, how exactly would I go about with this kind of a question. I understand that I will use the positive egde triggered and Q would be the clock. I would the connect the NAND gate with input 3 to clear to ensure that it will repeat the sequence but what of the provitions and would the sequence start at 15 and go down or would I also need to connect a NAND gate to PRE so it starts at 10. Any help would be much appreciated.

[@mariahh2034]

i understand why we removed Qa and Qc but how did we know they are not gate?

[@hunain57]

MAN YOU ROCK!!!!!

[@sriparno1146]

At 7:13 minute of the video why did you put the value of Qc and Qa by using a inverted NOT gate and taking the value to NAND Gate

[@KingTsunamy]

That means the counter is modulo 10 or modulo 9?

[@krishnabitling2447]

Why cant we use Qa and Qc

[@sayan486]

7:11. Why NOT gates are placed in reverse manner for Qc & QA?

[@Ali-xy9fi]

What is the equations for j, k input? Because if i apply k-map the answers are different then =1

[@nainaagrawal8314]

In cascading maximum count will be MN - 1 or (M - 1)(N - 1)?

[@nusratjahan9697]

Can you explain any explain in which clear is applied to particular filp flop.. Eg if 4ff are there and in only 2ff clear is used.

[@vasumahajan6407]

Where r we taking the output in cases mentioned in the starting of the video

[@anusharapaka2413]

Output is same Qa Qb Qc Qd But there due to 1010 -10 1 should convert to 0 so nand gate is used for Qd Qb in this case Dacade is for 0-9 decimals

[@theross327]

do u have the decade down counter? from 9 to 0. how to make the count start at 9, not at 15?

[@learn_what_I_learn]

Sir, but you used Q as clock in the down counter too. Then why did you say to use Q complement as clock.

[@nilouboe5096]

in that case you have to use Q complement as an output if you use Q an clock in down counter. its more convenient to stick with one output(Q) and just change the clock form Q to Q complement to switch between up and down counter.

[@amitbajpai8491]

Is there any difference between MOD 10 asynchronous counter and decade counter

[@bharathlr6739]

Both are same

[@ushoshibera7561]

If the preset is not connected then will it affect the circuit??

[@SayMyName811]

you are great master