Defining and routing PCB constraints for DDR3 memory circuits - Part 1: The theory

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Zuken

Zuken

Күн бұрын

Пікірлер: 3
@hassanrabbaniboyka
@hassanrabbaniboyka 4 жыл бұрын
one of the best lecture. please make more videos
@marshalcraft
@marshalcraft 7 жыл бұрын
Ok so the data lines are simply in series so they are strait forward. But the clock and address are in parallel so they have to be equal in each section.
@raimukherjee5806
@raimukherjee5806 Жыл бұрын
DRAM is fully parallel interfacing for data and addr both
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