DDR3 2133 Tutorial Intro

[@guillaume8437]

Brilliant video. I am in the midst of a design issue and seeing explanations like that helps a lot but in my case, it is not only a matter of PCB (routing constraints, passive values and location). These DDR chips are in interaction with an FPGA and then an ASIC based on this FPGA. There are lot more variables in the equation.

[@tfoxwa]

Agreed

[@elecengguide]

You have earned a new subscriber!

[@Litup14]

DQ bit order can be swapped as long as they remain the same byte group and also nibble group.

[@michelfeinstein]

Can we configure CDS and ODT by using simulations or do we need expensive high-frequency equipment to tune it in a real prototype?

[@gianlucalocri]

Hi Terry! great video! BTW have you ever made a part 3 of the series? Greetings from italy!

[@tfoxwa]

I am on to DDR5 at this point. Not even spending more time on DDR4 videos. Sorry

[@gianlucalocri]

@@tfoxwa no worries it is comprensible, thanks!

[@kumararvapally8904]

hi can you explain about 2n prefetch,4n prefetch,8n prefetch concepts in ddr technology ??

If I remember correctly, first data bit within the data byte can not be swapped. For exapmle, D0 can not be swapped with other bits, D8, D16,.. can not be swapped, too. I don't remember anymore where I got this information. Can you verify?

[@deniskolosov8368]

Hi Mübin if it's actuallity yet It's one of the most famous mistake with regard to ddr Yes, there are DDR controllers which don't allow to swap D0, D8 etc, but it's only particular cases for particular ICs. In common case, You can swap any bits within Bytelane With respect

[@terryfox6236]

DDR3-2133 means the fundamental clock is 2133/2 or 1066.5MHz The data is transferred at double data rate or 2133 mega-words per second

[@bazzmusic3125]

Same as old ddr3 I asume only 1066,5 MHz. Im running Kingston XMP 1600 at 800MHz

[@luisamedina6660]

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