Delay Calculation in Cadence Virtuoso.

[@kabandajamir9844]

The world's best teacher thanks sir

[@dr.hariprasadnaikbhattu]

Thanks for the appreciation

[@AnanayGarg]

this was very very helpful! i am in UCLA right now and your impact sir is global. Well done for the clear instructions.

[@dr.hariprasadnaikbhattu]

Thanks for your support

[@malehakim248]

This was hugely helpful to do my lab. Thank you.

[@dr.hariprasadnaikbhattu]

Glad it was helpful!

[@francorenatocampanavalderr2109]

Very nice explanation! Thanks a lot!

[@dr.hariprasadnaikbhattu]

Thanks and Welcome

[@babyushasunkara6293]

Sir, when i am calculating half adder and full adder i am getting delay in ns but in the papers values are in ps. Can you tell how to reduce the delay from ns to ps.

[@dr.hariprasadnaikbhattu]

Hi, it depend on the time period, width of the pulse and rise, times of the input. Also the signals that are used for measuring the delays.

[@arthuryang8461]

Thank you kind sir. Bless your heart. 🙏

[@dr.hariprasadnaikbhattu]

Thank you 🙏

[@babyushasunkara6293]

Sir, in pulse can i give pulse width and period in ns and delay,falling, and rise time in ps. Then calculate delay. Sir, i am getting spikes in the output will i run at every failing and rising edge of input. How to remove those spikes

[@dr.hariprasadnaikbhattu]

Hi, First question answer is OK and calculate delay. Second check the supply voltage.

[@gubbichow]

Hello sir. its a very helpful video.. For 4:1 MUX circuit how to find the delay? in cadence?

[@dr.hariprasadnaikbhattu]

Hi, delay calculation is same. Consider any 1 input and 1 output. Find the delay. Have a video on it watch it

[@r-rr3gn]

Sir, where can i take the capacitor

[@c-jay1014]

As per my knowledge you can take it from the library "Analoglib" (please correct me if I am wrong)

[@r-rr3gn]

@@c-jay1014 thank you I will check sir

[@c-jay1014]

@@r-rr3gn my pleasure

[@dr.hariprasadnaikbhattu]

Hi, some one answered

[@c-jay1014]

@@dr.hariprasadnaikbhattu sir did I say correct ?

[@SIEC_KUSUMAHS]

Sir can i give in vpulse and vdc specification in terms of nano instead of pico.. So if i gave in nano it will gave the same?

[@SIEC_KUSUMAHS]

I'm it will gave propagation delay?

[@dr.hariprasadnaikbhattu]

Hi, vpulse can be in nano second but vdc has to be V

[@dr.hariprasadnaikbhattu]

It can give delays

[@SIEC_KUSUMAHS]

Ok tq sir

[@dr.hariprasadnaikbhattu]

@@SIEC_KUSUMAHS welcome

[@happypurohit5836]

Sir I want to calculate delay of full adder circuit and average power of full adder in Cadence virtouso

[@happypurohit5836]

For single input and single output I got it. But sir in full ADDER circuit as we have 3 input and 2 output so how can I calculate average delay and power of circuit

[@dr.hariprasadnaikbhattu]

Full adder has three inputs. To calculate the delay any one input is sufficient either A or B or C.

[@PASUPULETINEERAJAPHD]

You explained very well sir. Can you explain how to calculate group delay in cadence tool, it would be very helpful.

[@dr.hariprasadnaikbhattu]

Hi Check for groupdelay in calculator special functions

[@PASUPULETINEERAJAPHD]

@@dr.hariprasadnaikbhattu Yes sir, Thank You.

[@hemanshichugh6982]

Very helpful video sir. Thanku for explaining. Could you please also upload a video on temperature analysis in cadence virtuoso. That would be a great help sir

[@dr.hariprasadnaikbhattu]

Hi, Thanks for your response. Definitely I will post a video on that.

[@ParminderKaur-zm4kw]

Sir how to remove those spikes in output???

[@dr.hariprasadnaikbhattu]

Which spikes are you talking about.

[@ParminderKaur-zm4kw]

At the transition from 1 to 0 and 0 to 1 of output

[@bruhbruh4137]

Where can i find the theory behind delay sir

[@bruhbruh4137]

Yes , please help me 😢

[@dr.hariprasadnaikbhattu]

Hi, there are many articles on this find it on google

[@dr.hariprasadnaikbhattu]

Hi, there are many articles on this find it on google

[@faizangokak3355]

Sir do the manual calculation and by using calculator(tool) delay differs ?

[@dr.hariprasadnaikbhattu]

I have showed the Tool Procedure.

[@பிருந்தாதஞ்சை]

Can u show the delay calculation for a coomparator sir?

[@dr.hariprasadnaikbhattu]

Comparator is analog design. Need to check.

[@பிருந்தாதஞ்சை]

@@dr.hariprasadnaikbhattu Sir will u provide your mail id?

[@பிருந்தாதஞ்சை]

I am watching your layout video and practising for inverter sir

[@dr.hariprasadnaikbhattu]

@@பிருந்தாதஞ்சை you provide your mail id

[@zenonisha505]

Sir could please suggest few research topic in antenna

[@dr.hariprasadnaikbhattu]

SIW antenna

[@aravindkota581]

Sir I want to calculate delay for level shifter,in placing marker I was confused whether it can be placed both input and output at rising or falling or one is rising and another one is falling could you please give response sir..

[@dr.hariprasadnaikbhattu]

Hi, delay is always between the input and output.

[@sasidharreddy2896]

Sir, I am research scholar in VLSI, please suggest research topics in VLSI, how can contact u?

[@dr.hariprasadnaikbhattu]

Where are you working. What is your specialization in VLSI.

[@sasidharreddy2896]

@@dr.hariprasadnaikbhattusir, SV university, Tirupati..... In mtech I did project on Low power VLSI... On HSPICE.... I want research topics in low power vlsi Or vlsi related topics sir

[@LavanyaVaishnavi]

how to calculate delay for NAND GATE??

[@dr.hariprasadnaikbhattu]

Process is same. Consider vin = a or b and vout =y

[@vaishnavitipireddy6450]

Thank you so much!

[@dr.hariprasadnaikbhattu]

You're welcome!

[@chethanar8805]

Hello Sir, While simulation, it's not opening outlog and waveform but it show successfully running in virtuoso window Can I know what has to be change in setting??

[@dr.hariprasadnaikbhattu]

Restart and check. See the ADE window for output enabled or not.