NAND LAYOUT /// VLSI LAB

VLSI lab for 7th Sen 2nd experiment Nand layout

[@zinhaboussi]

thanks for sharing , helpful

[@vlsiforrookies]

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[@bgs5570]

Do it for a 3 input nand gate, you can't clear drc or lvs errors completely! If cleared all errors ping me the comment section

[@PrashantKumar-wk3tu]

Can you do RC extraction after that, WLM, sta,timing analysis.

[@pushparaj3240]

Nice madam, why can't you use chain and fold options to combine the pmos. Which college you belong to. Thank you very much it will more help full to all.

[@mahammedfozail3693]

Very helpful... Thank you very much.

[@shiekhfahim6787]

Thank you ❤