Design Full Adder | Lets Learn Verilog with real-time Practice with Me | Day 11

[@avinsony10]

I am very glad to see your videos. I wish I had someone who could have guide me in my preparations. I also had similar utube channel with similar videos but with no subscribers. VLSI is upcoming field and will dominate cs in next few years .The only thing that concern is there are not right people with right skill to work. Syllabus and courses must be revised and be consulted with industry experts

[@sayandeepdey4]

please make the solution of adder-subtractor problem

[@S_R911]

In the top module (given in the question) the output port sum is declared as reg type which holds a value and can cause some wrong result in the outside world. But in verilog anything that is declared outside should be of net type only.

[@durgaprasadmaddala3727]

If fulladd4 module is written using always block then c_out should be reg data type or if fulladd4 module is written using assign statement then sum should of wire data type.