Simulation vs synthesis | Verilog synthesis using EDA playground | Day 18

[@buddepuchinna6609]

soon this gonna become a sensational reference love from NIT warangal ❤💘💘

[@NostalgiaT]

what is the use of multiplxer again?

[@shamsherlykhanpathan7489]

dude in the case statement we have to mention whether the condition is true or not...but y to declare them in bits 1'b1???? 1 means true and 0 means false ...so do we need to mention those true 1 and false 0 in bits always??????

[@heyitsmea8883]

It is showing no .svg file found. How to add

[@praxomacenterey6502]

Can you please notify us about VLSI job notifications for freshers in India. It would be very helpful Thanks

[@whyRD]

i thought of these , but you can easily get them in career sites of MNCs, and therefore i only shre infor which are hiddena and help you make your CV strong like traning , intersnship , marathon .... having said that i will ocnsider your views and will try send notification for job oppenings

[@rawsmackdown3376]

Brother,I am in the final year of my btech. I need guidence,I want to become a vlsi frontend engineer. I know digital electronics and started learning verilog . Si what should I learn more .. And what projects should i do ..and what tools should I use so I can become frontend engineer. PLEASE I NEED GUIDANCE

[@durgaprasadmaddala3727]

If you are aware of roles of frontend, design verification role has the most scope in India and for that role you need to know skills like system verilog and uvm methodology and any scripting language like perl, tcl and Linux commands and verilog and digital electronics are must.

[@rawsmackdown3376]

@@durgaprasadmaddala3727 design and verification I am looking for. But where should I learn all this uvm, system verilog, scripting languages so I can build a strong resume to crack a off campus placement.