Developing an SPI Controller for Zedboard OLED Display

[@utkarsh5165]

Very Good Explanation Sir. The way, he explains each States and its functionality is amazing. Very Logical lecture. Thank you Very Much Sir.

[@dheerajchumble5602]

Excellent tutorial sir. I am glad that i found it. Each part is explained in detail with support of good reasoning. Waiting for many more such videos.

[@jorch778]

You have very good teaching skills, nicely explained dude

[@Vipinkmenon]

Thank you..

[@DongNguyen-qq3in]

You have a great youtube channel, thank you for the detail and insight tutorials. I think the FSM process should use CLK, not SPI_CLK, because if the period of load_data is shorter than the SPI_CLK, then FSM will not work properly. Using CLK and falling edge of SPI_CLK to put data on.

[@SanjanaS-ot9xe]

sir.. could you please tell that how can we access the ddr memory in zedboard sir

[@sumone10]

Hello sir.. what is the code for a simple inbuilt spi controller in Xilinx sdk . Please help me out.

[@manojkumarponduru2684]

simply superb sir

[@ranitapaul29]

Thank you for the explanation. Can u provide us with the testbench of this ?

[@kayitbilgileri]

Thank you for your great tutorials. Why you assume that the Maximum SPI clock speed is 10 MHz, while it was written as it is the Minimum speed in the datasheet of the product? Thank you.

[@rakshaamunirathinam3488]

Is that the case with all fpga boards. I mean we need write code for all fpga boards in order to interface oled with the board. I have iCE stick 40 and i am just inserting the oled inti pomds of fpga iCE 40 stick

[@abahadoran]

Sir could create a wavediagram window explaining the state diagram ?

[@muratakjol1437]

Could you please consider to upload final verilog code for all such videos?

[@Vipinkmenon]

I have added the link in the description

[@SciHeartJourney]

There's already an interface for the SPI, why re-create it? I'm looking for a video that uses the BUILTIN SPI ports. Why is this so difficult to find?

[@Vipinkmenon]

Yes PS has an SPI and you can connect it to OLED through the EMIO interface.

[@SciHeartJourney]

@@Vipinkmenon, thank you. I just found out the hard way why we want to develop our own hard-coded SPI driver like this one: the Cmod-A7 does not have an SPI port (Microblaze). But I really need that SPI port on one, so this video just became one of my very favorites? I tried using the built-in QuadSPI, but you can't just pull one SPI port out it very easily. Maybe that is possible, but this method making our own SPI driver is more fundamental. Thanks for helping to open doors!

[@abahadoran]

Sir how did you know that the counter should count to 4 in order to achieve spi_clock with a frequency of 10 MHz ?

[@hthrun]

The input clock runs at 100 MHz and the SPI needs a 10 MHz clock. If you create a new clock based on another's positive edge it will be half the speed because you're only switching the new clock once a cycle. So that would give us a 50 MHz clock. To get the 50 MHz down to 10 we want to switch it every fifth time. The counter starts at 0 so to switch on the fifth time we have the counter go up to 4: count 0 to 4. It's tough to explain without a visual aid. Try comparing what I typed to his waveforms in the video. Let me know if I can clarify anything...

[@van-dungpham1201]

Can we use two SPI masters in the same design? For instance, I have two devices need to control, both of them are independent, it means they can send two different value to different devices at the same time? How can we implement this design?

[@Vipinkmenon]

Of course. You can just instatntiate two SPI controllers in a top file and during pin assignment, assign the pins where the two peripherals are connected. If you don't want to send data to the devices at the same time, one SPI controller is enough. It can have 2 slave select signals which can be controlled depending on to which peripheral you want to send data to.

[@van-dungpham1201]

@@Vipinkmenon Dear professor, as far as I know, Zynq can address only 1 SPI master at a time (we can only use SPI bus at one time). However, even I've tried with Zynq Ultrascale, but I could not get the good result (there is a different timing between two of SPI). Is there another solution?

[@Vipinkmenon]

If processor/software is controlling the SPI master, yes there will be slight delay between the starting of the two controller since software runs sequentially and it can configure the second controller only after configuring the first controller. If you want the controllers to start exactly at same time (like both asserting slave select on exactly same clock cycle), you will need some hardware to manage that in between. That means you cannot use the SPI controllers in PS and will have to implement them in PL. If you have using custom SPI controller (like the one I have written), you can easily do that. There can be a common control register for both controllers and software can write to that single register to start operation and both will start at the same time. If you will use Xilinx SPI IP core, you will need your custom hardware between processor and the SPI controllers. Software writes to your IP and it then controls the SPI controllers, which can happen in parallel.

[@nandoperu100]

Sir . Thank you for your video !!!. Could you make a video for I2C protocol in order to know how is the interchange data with slave device like RTC or Displays.. Thanks a lot again!!

[@Vipinkmenon]

Will try

[@Vas-vg4gd]

HI ,Vipin,Nice work really! .Could you also share as many videos as possible on the work you have done? Mostly on the constraints and larger design, Its good if you can guide on PCIE/ethernet/USb/Transceiver?

[@Vipinkmenon]

I will have on Ethernet and Pcie. But not on Zedboard. May be vc707 or vc709

[@KarthikReddy-tkr]

Bro.. please send zedboard data sheet link that you have used in this video.

[@Vipinkmenon]

cdn-shop.adafruit.com/datasheets/UG-2832HSWEG04.pdf cdn-shop.adafruit.com/datasheets/SSD1306.pdf

[@KarthikReddy-tkr]

@@Vipinkmenon Thank you but I want of zedboard document also

[@Vipinkmenon]

Just search in Google dear. Zedboard hardware user guide

[@KarthikReddy-tkr]

@@Vipinkmenon ok bro tq How can I contact you personally?

[@Vipinkmenon]

My email is in channel description

[@ViniciusCesarTech]

Thanks!!

[@dheerajchumble5602]

Sir, why don't u make series of such videos on this particular board for all peripherals and protocols and upload on Udemy. Newbie like me will get lots of benefit from it. It's not available anywhere.

[@Vipinkmenon]

Thank you for the suggestion. I will check it.

[@thanatosor]

- Where can I find any guide or document about FPGA ? ** A wild Indian guy appear **

[@Daniel456324]

This board is way overpriced. The Terasic DE1-SoC has similar architecture and logic gates for almost half the cost of this board.