Prof. I am not finding a series of video lectures (there were 6 videos) about using vivado to program fpga, you have explained in detail from opening a project to running an LED on the board (it was zybo I think)

Very Good Explanation Sir. The way, he explains each States and its functionality is amazing. Very Logical lecture. Thank you Very Much Sir.

sir I am using Edge A7 board I have already inbuilt ESP8266 WIFI , now I want to collect the data from another WIFI module to my FPGA how can create block level design

Amazing tutorial.. thank you for this video

This is the first time I've got this explained this well

Sir, thankyou for the video. I have a doubt, if we interconnect two ethernet ip whichbuses axi stream , can we send and receive ethernet frames? I tried it not working.

Your videos are all good and helpful for us to gain knowledge.

Thanks Vipin, your videos are so great

Which version you are using

could make it by using VHDL ??

thank you so much

greetings from colombia

Aslam o Alaikum! I am new on learning about AXI streaming interface.Can I get a helping material in this regrad that provide me beginner concept ?Plz

the same block diagram can be used in pynq environment without any changes?

but there is a better version to maintain integrity by using base64 rather then converting directly it will alpha and depth !!

sir, can you upload video for CNN on fpga

Glad to see you back

Happy that you are sharing your knowledge again with us. Thank you 🙏

Welcome back after many years! Good to hear you, even though the audio is not as clear as your previous videos.

I wished for such videos, thank you for your great videos

can you create similar video where custom IP packages are used

hello sir, Is there a way to connect the http websrver to a cloud server such as google cloud server storage to recieve files using http-client protocol?

Hi sir, i have STM boards with me, can i follow your video playlist to get handson on embedded systems

Long time no see, welcome back Vipin

Please share the code and slides of this tutorial.

Welcome back to your channel after long time. Please keep sharing such awesome tutorials.

Hello sir, how can I install this software model sim

Dear Sir I have built a module using PL part only to calculate the summation of Bytes. Now, I try to use the Zynq with axi-gpio to read the final value of the summation. I test each circuit individually, it is works correctly. The problem is that when I connected them together (the PL with PS), I did not get any results by the Zynq at the serial monitor. Please, if you can help. Thanks.

Dear Sir I have built a module using PL part only to calculate the summation of Bytes. Now, I try to use the Zynq with axi-gpio to read the final value of the summation. I test each circuit individually, it is works correctly. The problem is that when I connected them together (the PL with PS), I did not get any results by the Zynq at the serial monitor. Please, if you can help. Thanks.

Is it possible to get the slides?

9:00

I am using ZCU106, i am not getting the simulation result correctly, I am using 2022.1 Vivado

Hello sir. I run configure but my image data not transfer. My blurred.bmp file shows corrupted file. Can you tell me what will be the issue?

Thank you for this video, but I've used your example, and your algorithm stays in a loop of "status = checkHalted(XPAR_AXI_DMA_0_BASEADDR,0x4);"

16:10 how 6-input LUT is 16-bit deep instead of 64?

Hello Sir, What do we have instead of sdk in vivado 2023. How to open SDK in vivado 2023

Sir, i want to configure 4 channel XADC on bays 3 bord using microblage if please provide a IP based design for vits

How can I cite your work ?

sir but how to do it for video processing?

Why in 9:50 the fractional part 0.84 is represented as 1101011100 in binary?

Thank you sir..

Thanks bro❤

Hello Vipin Kizheppatt, Thanks for the tutorial, just wanted to share one issue what I have faced while execution on board. During modeCOntrol block instantiation, for these inputs -- we gave valid_vote_1, valid_vote_2, valid_vote_3, valid_vote_4 But some how that didn't worked and I was not able to see results in mode=1 .candidate1_button_press(valid_vote_1), .candidate2_button_press(valid_vote_2), .candidate3_button_press(valid_vote_3), .candidate4_button_press(valid_vote_4), So I tried to replace those four inputs like shown below, and it worked for me 😊😊 .candidate1_button_press(button1), .candidate2_button_press(button2), .candidate3_button_press(button3), .candidate4_button_press(button4), Thanks for the support !!

sincerely thank you!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Can i get to more information about edage detection

the files you provided in github are using RELU as activation function. I swapped it with sigmoid in the inlcude.v file and then ran the simulation, but the accuracy was too low nearing 15-17 range. Do i need to swap the activation function anywhere else?

bro can you show the result on the board

Thank you so much from these lectures, I learned a lot from you and very detailed explanation. I have accidentally found the problem that I trust maybe can improve your system. Almost errors when you transfer data between Pc and Zedboard through UART, that comes from xil_printf, print, or any c command code line who uses UART between Send and Receive Uart. I have did and seen, my totally printf line inside "image file". Because xil_printf, get_char, scanf of Xilinx functions base on Uart protocol. I did commented all xil_printf and no error happends.

Mr Kizheppatt, how can one prototype NoC (packet scheduling, etc) on fpgas? As switches in fpgas don't have transistors for logic like in the clbs, instead, only has minimal (pass/ access transistor), which are configured on device boot-up based on the bit-stream.

Hello sir i want use USB as device in PS what are the procedures