Digital Electronics: Difference between latch and flip flop Contribute: www.nesoacademy... Website ► www.nesoacademy... Facebook ► goo.gl/Nt0PmB Twitter ► / nesoacademy Pinterest ► / nesoacademy
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@its_argho6 жыл бұрын
the sound track used at the beginning of this channel's videos is "Be Thankful" by Shannon Kaiser and Kevin MacLeod, if at all some one cares btw.
@jpundarikakshakavipurapu2125 жыл бұрын
Yes. Some people do care.
@kishor-jena5 жыл бұрын
thanks I love that music and i wanted full track.. thanks a lot
@kishor-jena5 жыл бұрын
I did not get this track ;(
@adarshsasidharan2545 жыл бұрын
@@kishor-jena me too😂
@kishor-jena5 жыл бұрын
@@adarshsasidharan254 😁
@TechBitocracy2 жыл бұрын
What is the difference between latch and flip flop? When we use level triggering in the given circuit it will act as a latch, while if we use edge triggering by using a clock pulse to the circuit it will function as a flip flop. The latch is functional only when the signal is enabled, while the flip flop function when there is a transition b/w high to low or low to high in the clock pulse signal.
@pranavshukla20094 жыл бұрын
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions. Your lectures are great. Thank you so much for them.
@neerajkmanoj908 жыл бұрын
you're too good.... no confusions or flaws unlike the rest of the tutorials.... don't know how to thank you for the your effort you put together in making us comprehend. thanks again :-)
@ashhenriquez9182 жыл бұрын
I can listen to Neso Academy in my sleep and still learn something. Thank you!
@syedmkhan366 Жыл бұрын
Ye Kuch zyada nahe hogya bhai Saab hhh
@Anonymous-gt8zn6 жыл бұрын
Sir, my request is to add lecture no. in title of the lecture.
@NikhilKumar-pf2to4 жыл бұрын
its on photo displayed before playing video
@Roshenakthar3 жыл бұрын
Sir please do that. Because even if KZbin does not suggest the video, we can search
@debo9191 Жыл бұрын
@@NikhilKumar-pf2toyou mean thumbnail
@tarunkhandelwal110110 ай бұрын
@@debo9191😄🐥🐣
@mnoumanhaider48492 жыл бұрын
We are using the NAND gate but the eq you write for Q* and for S*is the eq for NOR gate Plz consider it
@AkashDixitShorts Жыл бұрын
Yes
@josphatmuriuki189 Жыл бұрын
yeah, he must have goofed
@danischn624610 ай бұрын
NAND gate is NOT(A AND B) and by DeMorgan's Law it turns to NOT(A) OR NOT(B) so technically the video is correct I think?
@nonu9828 жыл бұрын
Thumbs Up ! U guys are Awesome i have easily understood all the concepts you have been taught, your all videos related to multiplexer etc, are easily understandable. I completely appreciates your work ! No doubts and no questions at all! Great work man , keep going !(y) Thank your Very much
@hiteshyadav24238 жыл бұрын
Thanks a lot sir , the lectures are greatly helpful.
@kausikkar25874 жыл бұрын
Wow! U r awesome! Please explain Mechanics and Thermodynamics. Plss!!
@ahmedansari68273 жыл бұрын
that wud be so gr8
@parthabp28623 жыл бұрын
😂
@zynthos99 жыл бұрын
I thought in an SR latch when the inputs S and R (S* and R* in the case of the circuit you drew) were both 1, that the outputs Q and Qnot were invalid, or unknown. At 3:50 you seem to indicate that when S and R are both 1 the outputs are memory (or in other words they retain the same value). I thought that the case when S and R are both 0 was when the outputs were memory.
@zynthos99 жыл бұрын
***** Thank you very much for your response, I did not realize my error. These videos are great and I have learned a lot from them.
@stavrosmegoulis18795 жыл бұрын
dude i had the exact same question you are amazing
@ishan92092 жыл бұрын
1 can you please explain the ans of this que to me !
@ANUJKUMAR-ys6dy2 жыл бұрын
@@ishan9209 This is NAND SR latch, when both S & R are 1 then it acts as memory. Hope you get it!
@ajaybadigineni3 жыл бұрын
Thank you so much sir, you are helping a lot by your videos. We all are beneficial with your videos. Keep going sir, we all supports you. Thank you.
@tayyab.sheikh6 ай бұрын
Difference between LATCH & FLIP FLOPS : Latches are level triggered while flip flops are edge triggered.
@yungbanz4635 Жыл бұрын
What would happen if we were to use NOR gates for the S and R part (gates drawn in yellow) instead of NAND gates?
@devanandsharma66486 ай бұрын
Appki video mai apne lecture ko dikhya we bahut satisfy hue apki video se. Subscribe bhi kiye hai.
@markfinn8253 жыл бұрын
I prefer a latch made with one input of a OR gate as the latch Set input. The OR gate output is connected to the input of a AND gate. The other input of the AND gate is connected to the output of an inverter. The inverter input is the Reset input of the Latch. The AND gate output is the Latch output and it is connected to the other input of the OR gate. My understanding is that some integrated circuit outputs can not be connected together without measures being taken to prevent damage. I call the latch circuit above a reset master since a high reset input always results in a low output. To avoid confusion figure any part of the circuit that has a high output is in some way connected to that gates or inverters power supply positive connection. To be honest I have not even tested the above circuit but have tested its relay logic equivalent (which is slightly different).
@tusharsingla1708 жыл бұрын
why you said that latch works whenever enable is high whereas it is storing memory when enable is low?
@amandeo71855 жыл бұрын
Same question is mine also
@ani2000ify3 жыл бұрын
No it is not storing when enable is low, as there is NO OUTPUT
@rationalthinker96122 жыл бұрын
I am confused about that part where you are explaining the circuit being a Latch. You said that if the control input is enabled and if EN =0 then S* =1 and R* =1, this is what you called memory. However I thought if those inputs are both equal to 1, that this is an invalid state? Also you never defined what R* is equal to, is R* = R-complement + En-complement?
@dhanyabhatk3608 Жыл бұрын
see the prvs video on SR latch if it done using nor gate then 00 is memory and 11 is invalid if it is done using nand then 11 is memory here they are using nand so 11 is memory.
@nilanjandey2006 Жыл бұрын
@@dhanyabhatk3608 why would the circuit/latch not work when it is memory? it will not work when in not used state
@hakobmanukyan82333 жыл бұрын
Hi , I think you have done mistake by saying that S*=S(inverse)+En(inverse) , it should be S*=S(inverse)*En(inverse)
@nesoacademy3 жыл бұрын
There is no mistake, please check the circuit.
@lazysum2 жыл бұрын
apply boolean law - (AB) complement = A comp + B complement
@thetravellingengineer37352 жыл бұрын
Apply de Morgan's Law after that
@iambhushan4183 жыл бұрын
1 MILLION SUBSCRIBERS COMING SOON😁
@tanishksingh84436 жыл бұрын
We say Latch/Flip flops are one bit storage circuits,but in truth table,these circuits have two outputs ,one is complement of other.Thus they can store two bits ,then why we call them one bit storing circuits.Sorry if my basics are wrong,i am new to it :)
@tanishksingh84436 жыл бұрын
I sort of see it in this way,let me know if i am right.We never know the data we would want to work upon ,thus we use only one bit from flip flop or latch ckt,as we might know that next bit to be generated is its complement or not.If we use it another way we will have to install a mechanism to check whether we require the complement bit in our data or not,this will add to architecture and efficiency as flip flops will remain same in number and checking mechanism would just extra to the whole circuit thus decreasing efficiency.
@RiteshSingh-yp1sm10 ай бұрын
can you store 1 & 1 at the same time?
@sainithinmanthena97994 жыл бұрын
Sir please do videos on logic families...and memories
@amitchhachhia93637 жыл бұрын
sir due to your lectures I pass the B.Tech . Thank You Sir
@animeshanandcool7 жыл бұрын
same here..haha which college??
@yogendra5716 жыл бұрын
Latch is anyway part of flip flop, the basic storage element is latch only. The difference is in the controlling, latch is controlled by enable whereas flip flop is by clock.
@abhishektomar20825 жыл бұрын
@@PickledDragon why soo salty? getting a degree in btech isnt that simple it requires hardwork. If they get a job or not after that is none of your buisness. Stop being soo negative towards your own people shame.
@NandhanaSajin5 жыл бұрын
@@PickledDragon onnu podo
@PickledDragon5 жыл бұрын
None of the bitches understand my point. There are fucking WAY too many BTech bolders in the country. How many of them can articulate what they gobbled up during the course? Do you know what most of them end up doing finally? Go figure it out. BTech is nowadays like 10th grade in the 80s. Everyone has it.
@Official-tk3nc5 жыл бұрын
Sir . I dont know how to thank u. But ....... increadible effort
@user-mb9rv5sz9z10 ай бұрын
I am confused on the part where you said that the ckt is only operational when En is high, but then you show that it works when En is 0. Does this mean that the ckt only works when En is 0?
@kavyashree49908 жыл бұрын
Thank you sir, it was worth watching this video..
@dhirajkumarsahu9995 жыл бұрын
sir, at 4:43 you said that the circuit will only respond to the edge of the clock...but how does the circuit know that is should respond only at the edge because even in this case the output will change during the high period of the clock pulse.
@Khan__Usman6 жыл бұрын
i have a doubt ... lets consider edge triggering ....so you said that the curcuit will be active only when the signal makes a transition from low state to high state or vice versa.........so what happens to the circuit during high and low stages
@user-gx9lr2mh2i2 жыл бұрын
best channel on yt.
@easonlee40624 жыл бұрын
Thank you! very clear and impressive!!
@TheDipeshhh6 жыл бұрын
A flip flop is combination of latches in simple terms. There are other types as well but a positive edge triggered flip flop is a negative level latch connected to a positive level latch. This is some weird explanation. He is clearly confused.
@UpcycleElectronics4 жыл бұрын
His explanation works well for something like finding the difference between a 74HC373 and 74HC374. Everything has a lower order level of operation that can make higher level functions appear wrong in certain contexts.
@rhul00175 жыл бұрын
why we are using NAND gate and formulating the expression with OR operation??
@aftab_aaman5 жыл бұрын
it is the expression of NAND gate after using demorgan's theorem
@ammakutti13084 жыл бұрын
a.b whole bar gives a bar plus b bar
@DeepakKumar-dw1re2 жыл бұрын
बहुत मस्त समझाते हो आप।। धन्यवाद
@ramganesh72685 жыл бұрын
Q and Q inventory are the memory outputs but u are saying that S* And R* are memory and it is equal to the case 3
@sonalisinha15466 жыл бұрын
Sir, please upload videos on logic families
@omdumbre12102 жыл бұрын
the lecture are greatly helpful thanks a lot
@krishnavamsi25594 жыл бұрын
Sir,does clk mean it has only 50% duty cycle?if yes then can flipflop work with a random pulse?
@adedamolabasit20656 ай бұрын
It's no longer random once the clock is connected, the clock allows us to know when the circuit is functioning unlike before when it was totally random. As in now we know that the circuit is only operational when the clock signal is transitioning from high to low or from low to high.
@agstechnicalsupport2 жыл бұрын
Thank you for posting !
@chilinouillesdepommesdeter8196 жыл бұрын
Nand SR latch is in memory mode when set and reset are all 1.This is diffierent from the Nor SR latch.
@letsexpand6317 ай бұрын
well explained sir!
@JuanDVene6 жыл бұрын
Question at 3:53 Why is S* = 1 and R* =1 => memory? Shouldn't that create an invalid condition?
@buntychakraborty49699 жыл бұрын
You said that whenever enable is high then only ckt will work. but in the above video ckt is working when en=0. I am not getting this.
@farhanzia99416 жыл бұрын
Yaa that's a mistake, in this case the circuit is working for En=0. That means you can say that in this case Enable is an Active low signal.(That is just put a NOT gate in front of Enable signal and now the circuit will work whenever it is high)
@MrCahyo6666 жыл бұрын
He should use AND gate for clk instead NAND
@adarshsasidharan2545 жыл бұрын
Actually it is correct, if you notice when you take ebable = 0, it will make both S* and R* = 1 that is the memory state. And if you take enable= 1 it will give S*=S complement and R*= R complement, which is a valid operable condition for the latch. Even though you asked this question 3 years ago, there might be people like me reading the comments 😂. Hope this helps. Peace
@bhavsagar55 жыл бұрын
@@adarshsasidharan254 yup! ur comment helped me today just hours before my semester exam...😂😂😂
@adarshsasidharan2545 жыл бұрын
@@bhavsagar5 😂 I'm glad my exams are over
@ab_ab_c4 жыл бұрын
Wow.. you made something so easy--so complicated.
@SM-gn8er2 жыл бұрын
Wow you wrecked my university teacher in 5 minutes 32 seconds. Thank you so much, i finally learned this.
@s.m.seshareddy76992 жыл бұрын
Thank you soo much sir , very clear explanation
@flyinghigh34337 ай бұрын
thank you
@ahamedihthizam1474 жыл бұрын
this is not a flop flop, because still it is in level sensing mode,
@RobRobertRobbie7 жыл бұрын
Thanks for the video series! You saved my ass, my prof is terrible!
@nagarajugadela62057 жыл бұрын
please add floating point representation videos
@piyughosh45427 жыл бұрын
i dnt get it. why cant the circuit be used as a flipflop while keeping the clock as level triggered?
@thakermahek25014 жыл бұрын
Yes... Same question
@alvarojneto3 жыл бұрын
@@thakermahek2501 Because those are the definitions. I had the same question. My perception is that simple flip-flops and latches behave similarly in simple circuits, but differ in behaviour when circuits implement both edge-triggered and level synchronising.
@amitkumarsingh58227 ай бұрын
Nice clarification
@basicelectronics91827 жыл бұрын
please upload digital communication lessons sir
@UECAshutoshKumar Жыл бұрын
Thank you sir
@PrithaMajumder2 жыл бұрын
Very nice lecture...
@nevilholmes59004 жыл бұрын
thanks
@josuegutierrezpalma97818 жыл бұрын
Finally I get it, thank you
@jaiswalpriyam28116 жыл бұрын
Why we didn't use three input nand gate to control inputs ...I mean to add clock to ckt...??
@amitgarg81142 жыл бұрын
Sir, Which reference book you used for this topic .....Tell me because in some books there are different circuit of latch and it's explanation
@niamatullahbakhshi93719 жыл бұрын
sir! after explaining Enable : s* = E+(S-bar).. why did you use ( + ) here however the gate is NAND , not OR .. can you explain it to me .. Thank you ..
@dhruvdave51219 жыл бұрын
here s* = (e.s)' = e' + s'
@fijun15388 жыл бұрын
+photoyork : Bcuz if E = 0 then E' = 1 & according to this eqn : E' + S' , feed in the value of E' as 1 !! Then acdng to De Morgan's thm, (1 + Anything = 1 Only) , hence S* = 1 !!
@animeshanandcool7 жыл бұрын
no see 3:39 ,S*=1 when en'=1
@mdsharique96856 жыл бұрын
Monima Chowdhury ohh ya thnx mam
@HashmiSan6 жыл бұрын
There is a rule that says (AB)' =(A'+B')
@srividyakrishnakumar68955 жыл бұрын
Isn't it the same as a level-triggered flip flop? Why did you say that it will act as a flip flop only under edge triggering?
@sudhakarchekuri55897 жыл бұрын
what is the difference between Enable and clock?
@NLUSJPFRCH7 жыл бұрын
A clock(clk) is a pulse that happens at a certain frequency. This is the frequency the system works at. (The clk is continually sending pulses.) Every time the clk pulse enters the flip-flop it is able to change state depending on the input values. While the enable is a signal that enables the flip-flop to either register an input or not. If enable is 0, the output will always be 0. If the enable is 1 then the output depends on the input. The enable has no frequency and can be chosen by the user, or machine. While the clk is always running and sending pulses.
@sang62587 жыл бұрын
Then what about enable?
@jagnoorsingh20316 жыл бұрын
Enable signal is different from clock. It isn't regular like clock which suggests that it is generated by some other logic. The device will work as long as the enable is positive. On the other hands, clocks are regular and the flip flop works on the edge triggering of clocks.
@BenardOnchieku-ny5qc Жыл бұрын
Very good presentation H/w option B
@haroonkhalid575 жыл бұрын
how output will change in positive edge triggering flipflop when it goes from lower to higher state (0 to 1). why output will not change in positive edge triggering flipflop when it remains in higher state(1)? , as the flipflop will be active when its clock input or enable input is in higher state(1).
@hemasundar35147 жыл бұрын
nice explanation
@soumyokantichakraborty55126 жыл бұрын
please make video on ..linear integrated circuit opamp and ...ce cc cb amplifier
@rajuk96506 жыл бұрын
what is the maximum frequency can be given to a flip flop ?
@saqlainahmed41973 жыл бұрын
Sir make a clear video on active low and active high enable input
@sowmyashetty5336 жыл бұрын
sir is there any other difference between flip-flop and latches
@madushanprathap99013 жыл бұрын
Thank You
@HelloWorld40408 Жыл бұрын
Thank you
@grandson_f_phixis9480 Жыл бұрын
Thank you very much sir🥳🥳🥳🥳
@debasismohanty12125 жыл бұрын
when we apply clock for flip flops what is the input send to the nand gate while leading edge/falling edge case?
@Mr-Producer.7 жыл бұрын
sir, if clock is what is concerned for determining flip flop or latch why is the circuit for latch operational for en =0 in case of latch as it should have been en=1 as per your words
@AnoNymous-po5sx3 жыл бұрын
When enable is zero, the Q and Q' won't change. It simply means that we don't wanna change the Q and Q' until we need to update. It doesn't mean that the device stopped working. When enable is one, the Q and Q' change the state based on R and S values. I know it's too late. But wanted to reply just for my reference. 😂😂😂
@mrmakra-eo1kx5 жыл бұрын
In that circuit when you show the difference between latch and flip flop i don't understand why did you used nand gate in front of the clock wire ( when the clock is high or on after the nand gate it should be off and i don't want that right ).
@enjoyingyourself6 жыл бұрын
Sir, is in rectangular signal or duty cycle is not 50 percent, if edge triggering is apply then, it is flip-flop or latch?
@muskanrath71255 жыл бұрын
Sir, why is S*=1, R*=1 when EN=0
@ayushdhupar34105 жыл бұрын
WELL DONE
@amyouse50207 жыл бұрын
sir. excuse me ,the the gate that obtain s* is NAND there for S*='s.en or i am wrong
@risabh84085 жыл бұрын
expand it using De Morgans you will get the same
@anym-san4 жыл бұрын
It's S* = (S . En)' = S' + En' So it's like that
@basicelectronics91827 жыл бұрын
sir please upload lessons on digital communication and also tutorial problems in digital communications
@GossipGirlcorner5 жыл бұрын
Awesome sir
@hitman27545 жыл бұрын
At 3:21 how you are using or gate formula
@Chopper1535 жыл бұрын
Apply De'Morgan's theorem to nand gate. Then u will get this.
@sujithmeena38875 жыл бұрын
Well understanding...
@bidaarle5 жыл бұрын
invite me when you win the Nobel prize
@maheshnayak29415 жыл бұрын
Abdullahi Mahmud what😂???
@harcharansingh19973 жыл бұрын
Wait , what ? 😂😂😂😂😂😂
@adedamolabasit20656 ай бұрын
Please, i don't understand the part about enable being high or low for S star.
@khadijaasif28912 жыл бұрын
Thnks for your guidance. May ALLAH bless you.
@PankajKumar-tr2lt4 жыл бұрын
please help regarding this, it is wrong in video, caus it means in case of enable equals to 1, its not latching, its rather transitioning in different according to S and R value, so when enable is 0 then only it will be S and R latch, so in the lecture he was telling when enable is 1 then it will be working is latch,
@naganandhinikanniappan91824 жыл бұрын
exactly i had the same doubt
@audience40175 жыл бұрын
@3:12 Nand Gate op= ~S* and ~En* Its Not NOR gate.
@alphasatari5 жыл бұрын
Audience Output of NAND gate, S*=(S.En)’ You can convert it into another form using De Morgan’s law S*=S’+En’
@tanmoydutta58462 жыл бұрын
Won't the flip flop as enabled by the clock at 5:05 be functional only when the clock is high? Like I don't get why is it edge-triggered/edge-sensitive in this particular design. Even with a clock, the circuit should remain functional only when the level is high, and not just during transition. Am I right? 🙁🙁🙁🙁
@shadowmaas3 жыл бұрын
Bro you have used nand gate and the put of the nand gate is y=a.b But you have taken the formula of nor gate🙄 And you have told that we will consider memory when s=0 and r=0 but you have not done that please clarify my doubts
@minxxdia11323 жыл бұрын
hey, so the logic expression for nand gate is y = (a.b)' and using de morgan's laws the output can be written as y = a' + b' also, there are two ways you can implement the sr latch, the nor and the nand implementation. in his previous video he explained the nor implemented and that's when r=0, s=0 is considered the memory state. in the nand gate implementation, memory state is when s=1, r=1 hope this helped :)
@rajvirdi18167 жыл бұрын
can u suggest A GOOD BOOK also?
@rewalientenokurki22297 жыл бұрын
which flip flop or latch circuits we use in servers . I am asking because in server we have to use flip flop without delay .
@csworld93193 жыл бұрын
What is operational and functionsl in given lecture ???
@barsilgen120 Жыл бұрын
Thanks
@direnbhatsavesoil96287 ай бұрын
3:21 You said "If the value of En = 1, this means that S* is S' ". How come? S* depends on En and S. So, just by knowing En, we can't predict the value of S*.
@vamsidharalluri79666 жыл бұрын
Sir i have one doubt .latch and flipflop both are used to store the bits then why are we not using latch instead of flipflop.
@DupczacyBawol7 жыл бұрын
but NAND gate outputs a 0 when you enable it. zero is false, and it all works upside down. when you say 'enable' you really disable the positive output, right?
@achiever1004 жыл бұрын
Superb
@naveenkumar-yf7si5 жыл бұрын
Thank u sooooo much sir .😊
@ravireddy077 жыл бұрын
why we use Enable Pin in this Circuit..??? What's the use of it..?? Suppose...Clock Set's the Certain Frequency for changing the Time of output's...