Introduction to SR Flip Flop

Digital Electronics: Introduction to SR Flip Flop.
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[@akhileshcruizes3637]

Those who have confusion in TT. In SR latch video we use a NOR gate but in this video we use a NAND gate that's why the value of Q and Q' seems to be reversed.

[@bhaskarbhar237]

Yes the TT seems to be reversed. He has used NAND in this video, so as per that when S and R are both 0, that will be a forbidden state or not used state. He made the TT for NOR gate.

[@Youba05]

@@bhaskarbhar237 you're wrong, he's using it for the nand gate and it's correct

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If you know previous concept no need to go back sucker

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[@samhblackmore]

Excellent explanation, could not have been any clearer!

[@xXmayank.kumarXx]

Lecture 119 is actually "SR Latch" (150th in the playlist)

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lecture 145

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what i haven't understood in class..its very clear to me after seeing it..best explanation ever about digital electronics..thank you sir

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[@muhammadamir-fq5nl]

Thanks alot :)

[@sukhmanpalvinder4273]

Best ever lecture for digital electration....after watching your lecture I understood very well but I have a one question why are u using level triggered in SR flip flop

[@OmniaAdelAhmadMuhammad]

Note: This TT is for SR latch using NOR gates not NAND gates.

[@ahnafhassanar77]

sir please use the lecture number too when naming the video.

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kzbin.info/www/bejne/fovKaJmEqpKfaJY watch the videos in sequence.

[@sarwarishupadhyay8773]

LECT 119 : kzbin.info/www/bejne/oaWblWZ5jrx6fpY

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Best lecture i have ever heard.It really helped me lot.

[@shihabkabashi7215]

Dr. you said FF are edge triggered however, you're using level values. is it right?

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Sir ur teaching is excellent ❤ but please Explain as much as in a simpler way.. 🙏❤

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Good , Thank you for taking interest for posting this video ..... keep posting

[@Goshens24]

Thank you for this explanation. Very clear and understandable. I have one question though. What about when you are told that there is an active high enable input or active low enable input?

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[@brd8764]

The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential logic circuit possible. ... A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its opposing inputs and is commonly used in memory circuits to store a single data bit.

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[@arnav9248]

In this lecture you are saying SR latch for nand gate table is giving 0 1 output of input 1 0 but in lecture no.119 u have written 0 1 is giving 0 1 in SR latch for nand gate. Kindly clarify

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[@olimpiuonut2853]

Great lectures. Could you put the number of lecture in video title? (in this lecture 124 you reffer to lecture 119 )because is difficult to find them since lectures are not uploaded in order.Thank you.

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[@Opacity5]

i didnt get whats clk 0 and 1?? how can you relate 0 and 1 to level or edge sensitive? please reply

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You deserve 10M subscriber

[@hemantsood9579]

sir we know that flip flop is device carry 1bit of information. So where we store 1bit value in S input or R input ?

[@sanjaypaul5898]

can we use NOR Gates instead of NAND in S-R FlipFlops?? what will be the truth table then??

[@ajaymaurya5794]

this is also an sr latch with clock being considered as an enable input.

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bundles of thanks for spreading knowledges !

[@haider4899]

In Digital Design by Morris Mano, this is called SR Latch. its the same thing, don't worry.

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hey there ! thank you posting videos they are of great help, please post the lecture for dac and adc as soon as possible. thank you

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Your vedio lecture helps lot 💞thank you sir

[@siu281]

I didnt get one thing. It was mentioned in the previous video that the difference between SR latch and SR flip flop is that the former is level triggered while the latter is edge triggered. But isnt level triggering being used for SR flip flop here? And secondly, does SR latch have no clock input?

[@atharvapuranik5172]

Yes, SR latch does not have CLK input so it updates the output immediately as input changes while a flip flop updates the output only when the CLK signal is changing from low to high (leading edge) or high to low (falling edge) as it is edge triggered.

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saving my life rn

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[@roshankumar2642]

A flip-flop is edge triggered.then why are you using level triggering in SR flip-flop?

[@amentothatt]

+Roshan Kumar you are right. He has a SR latch with clock signal but not SR flip flop

[@agarvipul]

Roshan Kumar u can consider it as level triggering...since there is no feedback from output to input..level or edge is not important here

[@anupamarajanna171]

Very good question. What is explaned in this video is SR latch and not flip flop. Consider reading page number 196 from Digital Design from M. Morrris Mano.

[@komalkaur9074]

sir first of all thank u very much for all d videos u have uploaded.. u r d best.. sir, plz tell dat flip flop can store multiple bits or not?

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[@Shivamsingh-ny9ps]

Sir in previous lecture u told that flip flop is edge sensitive but here u have explained characteristics table with level of clock.???

[@pi-tech1817]

Very well explained sir, understood the concept , thank u

[@TechBitocracy]

SR Flip Flop When we attach clock pulse to SR latch it becomes SR flip flop, SR flip flop is an in-memory state when Either clock pulse or SR has low low input. Edge Triggering Method is used for Triggering the circuit. and so on

[@Aweheid]

I think R*&S* should be R(bar)& S(bar) because when we enter 00 in NAND gate that always will give us 1 to Q and Qbar so we should start from 11 not 00 , am i right ?

[@ankithprabhu4552]

sir in lecture 119 you have explained sr ff using nor gates but in this video you used nand gates which confused me for a while..ps add an annotation for other viewers, for them to understand better...anyways thanks a ton!!!

[@ankithprabhu4552]

what i feel is using nand is better as it retains the memory when the clk is 0 which is what should happen in general memory systems

[@richaambatipudi]

He actually did use NAND gates too. But he didn't explain it since the method is basically the same as that of NOR. He did give the table though. If you've paid attention to NOR gates, you should be able to solve NAND just as easily. Cheers x

[@richaambatipudi]

He actually did use NAND gates too. But he didn't explain it since the method is basically the same as that of NOR. He did give the table though. If you've paid attention to NOR gates, you should be able to solve NAND just as easily. Cheers x

[@ankithprabhu4552]

i know..i just mentioned that it could be confusing :s anyways its good to see replies on youtube Cheers xP

[@supriyasuman3815]

Richa Ambatipudi yaa really...it was in short but carried the same process as nor gate

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