DVD - Lecture 2b: Verilog Syntax

[@AdiTeman]

Errata: At time @23:24 the default state of the Mux should (of course) be 1'bx (and not 4'bx on a one bit signal). Thanks @atharvaagiwal6051 for paying attention to this.

[@MinhNg180]

I didn't skip any second, really well explained

[@AdiTeman]

Thanks!

[@atharvaagiwal6051]

In the default statement the output should be 1'bx. For 4:1 mux

[@AdiTeman]

Haha, Great catch! This slide (and video) has been around for quite some time and no one ever pointed that out. This is not an error, per se, since it's just an X (and 4'bx is basically the same as 1'bx) and the simulator and synthesizer would (hopefully) disregard this, but it was for sure unintentional in the slide. Thanks for finding this. I will pin the errata!

[@VichhayChhuon619]

Very well explained course. Definitely taking this till the end :) Absolutely loving it.

[@AdiTeman]

Great to hear!

[@marioalvarado3347]

Thanks for the lectures. The playlist is very informative. How would you go about designing a programmable logic controller aka PLC?

[@AdiTeman]

Hi, I think that PLCs fall into a very different category. They do not have the flexibility of ASIC design and are usually limited to a clear toolchain and programming flow. So Verilog would not be the language to program them. Instead, they use things like Ladder Diagram and Structured Text.

[@AlJay0032]

What happens when blocking and nonblocking assignments are intermixed?

[@AdiTeman]

Chaos... :) The truth is that there is pretty much a clear "definition", but zero-delay simulation can interpret them a bit differently. Things "may" work in simulation, but RTL simulation may not be equivalent to the gate level implementation and it also may depend on the synthesizer. Bottom line - don't do it!

[@venkateshiyer5073]

Loved the session

[@AdiTeman]

Great!

[@mcorrive12]

Thank you!

[@AdiTeman]

You're welcome!

[@nandinichalla686]

It is very useful thank u sir

[@AdiTeman]

Always welcome

[@SakshiBhoosa-xc7mk]

Can we get jobs in Rtl design by studying from this course?

[@AdiTeman]

Hi, I think that's a difficult question to answer. This is a very short RTL tutorial - but it is indeed a good start. I think that you would need to practice writing a lot of RTL before getting accepted to a job based on your knowledge and there is a lot of good material around the web. But starting with this lecture, it will help.