DVD - Lecture 3a: Logic Synthesis

DVD - Lecture 3a: Logic Synthesis - Part 1

Рет қаралды 10,890

Adi Teman

Күн бұрын

Пікірлер: 13

@yemingli 11 ай бұрын

it seems like the delta is the next state function, and lambda is the output function?

@AdiTeman 8 ай бұрын

That is very correct (interesting that no one has paid attention for the many years that this slide has been available :) I will pin an errata. Happy New Year!

@yemingli 8 ай бұрын

Thank you for your reply. I enjoy learning from your lectures, and thank you very much for sharing your knowledge and lectures with those who want to learn. Thanks again : )

@yemingli 8 ай бұрын

Happy New Year to you and your family, too. @@AdiTeman

@AdiTeman 8 ай бұрын

Errata: On slide 5 (@13:09), delta should be the next state function and lambda should be the output function. (Thanks @yemingli for paying attention to this)

@embeddedenthusiast7121 Жыл бұрын

Thank you❤

@AdiTeman Жыл бұрын

You're welcome 😊

@whateverittakes9000 Жыл бұрын

Hello, thank you for the lecture series. I have one question. Consider if there's a simple OR operation of 3 bits and I have provided only 2 of the 3 inputs in the sensitivity list., I know that when the 3rd input bit will change, it will not trigger thevprocess block. But what about the GTL,?when it will be synthesized, obviously it will be a 3 input OR (or combination 2 2-input OR) and will work fine. So why was this "sensitivity list" thing incorporated in a HDL?

@AdiTeman Жыл бұрын

Hi Debtanu, This is exactly the problem. No - the behavior you describe should not trigger on the third input. Therefore the synthesis - which must be equivalent with the RTL - will infer a latch that will block the third input unless one of the other two inputs toggle. So it won't synthesize to a simple 3-input OR. In some cases, for example FPGA synthesizers, this may synthesize to a 3-input OR, but this is incorrect behavior. While it may happen because a certain function implementer decided that this was "probably" the intended behavior, an industry-standard ASIC synthesis tool will not cut such corners and a logic equivalence formal verification will show that the gatelevel differs from the RTL. As to "why" there is a sensitivity list, I cannot say what all the historical reasons for designing the languages as they were designed, but (a) I am sure there were pretty good reasons at the time and (b) to "right the wrong" - or at least make the common case easier and less buggy - the "*" was introduced in later Verilog versions.

@veliogut358 Жыл бұрын

Could you share the example files for synthesis? I wonder that entire folder because I understood that which parts means what but I didnt concatenate

@AdiTeman Жыл бұрын

Do you mean the synthesis scripts? No, unfortunately, I do not have permission to share these currently due to various IP issues. I am working on getting permission, but the chip design community is not always open to this...