DVD - Lecture 6c: Floorplanning

  Рет қаралды 7,495

Adi Teman

Adi Teman

Күн бұрын

Пікірлер: 5
@rogerfederer6456
@rogerfederer6456 2 ай бұрын
Hello Professor Teman, what is the reason behind placing the power-hungry macros away from the chip center for wire bond in the slide on Hard Macro Placement. What role does position have in the therma aspect? Whats the relation to the wire bond? Does it matter if it is a BGA?
@AdiTeman
@AdiTeman 2 ай бұрын
Hi, sorry for my belated answer. The main reason would just be to get them as close as possible to the source of the power supply (i.e., power pad), so the IR Drop would have minimal effect.
@rogerfederer6456
@rogerfederer6456 2 ай бұрын
What might be the use of a routing blockage?
@AdiTeman
@AdiTeman 2 ай бұрын
Thanks for the question. This is indeed a good one. There are several reasons for blocking routing, but to give you a few examples: 1) Leaving a "feedthrough" channel for a signal to be routed from the toplevel. Say there is an analog input that needs to be fed from a pad to a block that is blocked by this macro, then we can leave a channel to route the signal when the toplevel routing is applied. 2) Special circuits (usually analog) that don't want to have noisy digital signals running on top of them. 3) A hierarchical macro is only provided a certain number of metals to use (the rest being allocated to the top level). In this case, you would set an attribute for top level routing, but you could also apply a blockage to be sure the tool didn't do anything funny (which these tools are known to do). I'm sure there are many more examples, but these just came off the top of my head.
@rogerfederer6456
@rogerfederer6456 2 ай бұрын
@@AdiTeman thanks for the clarification
DVD - Lecture 6d: Hierarchical Design
10:00
Adi Teman
Рет қаралды 4,8 М.
DVD - Lecture 6e: Power Planning
19:50
Adi Teman
Рет қаралды 8 М.
Sigma Kid Mistake #funny #sigma
00:17
CRAZY GREAPA
Рет қаралды 30 МЛН
Beat Ronaldo, Win $1,000,000
22:45
MrBeast
Рет қаралды 158 МЛН
Cheerleader Transformation That Left Everyone Speechless! #shorts
00:27
Fabiosa Best Lifehacks
Рет қаралды 16 МЛН
PD Lec 16- Floor-planning [part-2] | VLSI | Physical Design
7:01
VLSI Academy
Рет қаралды 22 М.
DVD - Lecture 8a: Clock Tree Synthesis (CTS)
19:19
Adi Teman
Рет қаралды 6 М.
DVD - Lecture 7b: Random Placement
14:35
Adi Teman
Рет қаралды 3,5 М.
DVD - Lecture 8b: Clock Distribution
17:00
Adi Teman
Рет қаралды 4,7 М.
Physical Design - 1e - ICC2 - Floorplan 1 - Different Stages
9:22
VLSI EXPERT (vlsi EG)
Рет қаралды 15 М.
DVD - Lecture 7e: Placement in Practice
12:28
Adi Teman
Рет қаралды 3 М.
DVD - Lecture 7c: Analytic Placement
14:51
Adi Teman
Рет қаралды 3,1 М.
Sigma Kid Mistake #funny #sigma
00:17
CRAZY GREAPA
Рет қаралды 30 МЛН