DVD - Lecture 6e: Power Planning

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Adi Teman

Күн бұрын

Пікірлер: 21

@DSPY1009 2 жыл бұрын

awesome source for anyone who is aspiring / interested to work in Physical Design domain

@AdiTeman 2 жыл бұрын

Thank you for the kind words.

@张雨田-z5y 2 ай бұрын

Sir thank you so much for your vedio provided. I got confused at 8:09 of the lecture. I consider the IR drop calculation should be irrelevant with width of the rails, only related with the square resistance and the max current as in calculation of R the width is on Denominator while for I max calculation the width is on Numerator . So why should we wider the power rail ？

@AdiTeman 2 ай бұрын

Hi. Your confusion comes from me combining two separate phenomena in this example. First, IR drop - here, I just measured the resistance. The resistance is for sure not "irrelevant with width of the rails" because the wider the wire is, the "fewer squares" you have. My best way of explaining this is a highway with cars running on it - the more lanes (width), the more cars can pass at once (current) or in corollary, the lower resistance. The reason we care about resistance is "IR" drop (Ohm's law: V=IR), so we also need the current. If the current is tiny or non-existent, then "who cares" what the resistance is, right? So in the second part of the exercise, I tried to get a representative number for the current to understand if the resistance we calculated is problematic. How do I get such a number? Are we conducting mA, uA, nA, pA? So I used the number for the maximum allowed current, which is defined by EM constraints. For EM, we are also limited by the current density, which is the current divided by the area that the current goes through. Since the thickness of the conductor is given (like in square resistance), we only need a number for current divided by wire width and that is given as 1mA/1um. Since we chose a wire with a width of 100nm, we got a maximum allowed current of 0.1mA. Now, assuming this could be running through the wire (if it's allowed, then we're going to drive it through, right?!), then we can find what the voltage drop is going to be. I hope that cleared it up.

@张雨田-z5y 2 ай бұрын

@@AdiTeman thank u somuch! I consider I understand now

@Torchl146 2 ай бұрын

Did you already gather experience with AI in the floorplan creation or at your institute ? Is there already a Cadence tool for this? I feel like there is a lot of manual guessing in this physical design step that should/could be optimized with metrics. Also I heard about Google doing exactly that its called AlphaChip if i remember it correctly

@AdiTeman 25 күн бұрын

Hi @Torchl46 - excellent comment. My answer is... sort of. Indeed, there is a lot of work on AI for chip design over the last few years and it's a super interesting domain. The best known work is, indeed, AlphaChip, which kind of kicked this whole field into gear. But it wasn't started in a vacuum and it has been followed by a real ton of great innovation in all fields of chip design. Furthermore, the EDA vendors are also providing AI-driven solutions in their commercial tools. Why do I say "sort of"? Because I have a student who works with the AlphaChip team and has been able to run the tool and evaluate it. But I haven't personally (actually, at this point in my career, I don't get my hands wet with "real engineering" that often...). I will tell you that I ask around quite a bit and I don't find many backend teams in industry working with the new tools yet. I imagine it will come, but it's sometimes hard to steer this very heavy ship that has been moving in one direction for many years ;)

@rogerfederer6456 Ай бұрын

What does "provide return path for signals" mean, since current has to flow in a loop anyway

@AdiTeman 25 күн бұрын

Yes, that is the meaning. We need to provide both the source of the power (i.e., VDD) and the return path (i.e., GND).

@rogerfederer6456 25 күн бұрын

@AdiTeman is it even possible to not provide the return path. Where would the current flow then?

@kabilansenthilkumar7644 Ай бұрын

how did the power rings are getting the power.How to connect ports/terminals to the power rings.

@AdiTeman 25 күн бұрын

So I'm not sure I'm answering the exact question you're asking, but I'll try. The power to the chip comes in from outside the chip (usually). There is a power supply or battery on the board with regulators that bring the voltage down to the DC voltage required by the chip. These are connected through pads to the chip (see the later lecture on I/Os and packages) and from there are connected to the power rings. That is at the full chip level. If we are designing a block and not the full chip, then we will have to connect the power rails from the fullchip level to the block power rings and power grid (stripes).

@abdelazeem201 2 жыл бұрын

Hi sir, First of all, thank you very much for the course. I enjoyed every minute of your Videos. secondly, I have a doubt if we plan the power for a higher metal layer, how do standard cells get its power, which it planned in lower metal layers? I think we can use vias until we reach to the M1, but this will consume more power and affect reliability, is that true? secondly at what metal layer will be the VDD/GND net/pin exactly? lastly, is it preferred that the metal layer in the Power planning to be vertical or horizontal?

@AdiTeman 2 жыл бұрын

Hi, I'm so happy you are enjoying the videos. Here are the answers to your questions: 1 and 2) Yes, indeed, the power is usually routed in a grid, starting from the top metal layer and through some of the lower layers, until finally connecting to the "follow pins" or "VDD/GND rails", which are part of the standard cells. In most traditional processes, these are on M1, though I have seen libraries that use M2 follow pins. It is very common to run the grid on the top two metal layers which are really thick, then go down large Via stacks to a much lower metal (e.g., M3 or M2) and then connect frequently from this metal to M1. However, different companies have come up with different methodologies for building such a grid. Regarding the question of power and reliability - actually, no, these are not the concerns here. The via stack uses big matrices of vias, so they are not very susceptible to reliability problems. In addition, this is a net that is supplying power, not wasting it through toggling or leakage. The main concern is the IR Drop - the vias have resistance that can cause the voltage level that reaches the standard cell to be affected. However, that is why multi-via arrays are used. 3) The connections are usually M1. These are usually horizontal stripes (called "rails" or "follow pins") that go across the entire row of standard cells. The entire stripe is marked as a PIN so the higher layers of the power grid can easily drop vias down onto it. Hope that answered your questions. Adi

@abdelazeem201 Жыл бұрын

@@AdiTeman thank you for your reply and detailed explanation. I have another question. is there any advice about How to choose the number of core rings/straps? also the width and spacing of rinds/straps? I know we can play around and make an estimation like we can get the static and internal power from synthesis tools like Genus/DC, and we can get dynamic power from simulation like we can run the simulation with SAIF/VCD file and get the activity factor and go for power analysis tools like PrimTimePX and estimate the dynamic power, but is this what is the real happened in the industry? or there are tips and tricks from experts like you? or it is just like "black magic" and we have to play around and just do an inspection then try it and then run IR drop analysis, then if it's acceptable and within the range, we can go through the whole steps, and if not then can return and adjust and so on...